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    NESTABLE READER-WRITER LOCK FOR MULTIPROCESSOR SYSTEMS
    1.
    发明公开
    NESTABLE READER-WRITER LOCK FOR MULTIPROCESSOR SYSTEMS 审中-公开
    对于多处理器系统嵌套READER / SCHREIBERLOCK

    公开(公告)号：EP1247170A4

    公开(公告)日：2006-12-13

    申请号：EP01903009

    申请日：2001-01-09

    Applicant: IBM

    Inventor： MCKENNEY PAUL EDWARD

    IPC: G06F15/177 ,  G06F20060101 ,  G06F9/00 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F12/06 ,  G06F15/163

    CPC classification number: G06F9/52

    Abstract: A nestable reader-writer lock minimizes writer and reader overhead by employing lock structures that are shared among groups of processors (24) that have lower latencies. In the illustrated multiprocessor system having a non-uniform memory access (NUMA) architecture, in a first embodiment each processor node has a lock structure (83) comprised of a shared counter (84) and associated flag (85) for each CPU group. During a read, the counter can be changed only by processors within a CPU group performing a read. This reduces the reader overhead that otherwise would exist if all processors in the system sharEd a single counter. During a write, the shared flag can be changed by a process running on any processor in the system. The processors in a CPU group are notified of the write through the shared flag. This reduces the writer overhead that otherwise would exist if each processor in the system had a separate flag. The number of CPUs per group can be varied to optimize performance of the lock in different multiprocessor systems. In a second embodiment a global counter (91) indicates the number of active reader threads that are not accounted for in the per-CPU-group counters (94). This permits a reader thread to read-release a lock without determining which processor that thread was running on when it last read-acquired that lock.

    QUAD AWARE LOCKING PRIMITIVE
    2.
    发明公开
    QUAD AWARE LOCKING PRIMITIVE 审中-公开
    QUAD AWARE锁定原语

    公开(公告)号：EP1358529A4

    公开(公告)日：2008-06-04

    申请号：EP01985598

    申请日：2001-12-28

    Applicant: IBM

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F9/46 ,  G06F12/08 ,  G06F1/00 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy (910, 920), and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive (800) and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

    Optimizing grace period detection for preemptible read-copy update on uniprocessor systems
    3.
    发明专利
    Optimizing grace period detection for preemptible read-copy update on uniprocessor systems 有权
    优化周期性检测对于联合处理系统的可循环读取更新

    公开(公告)号：JP2010033554A

    公开(公告)日：2010-02-12

    申请号：JP2009148307

    申请日：2009-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHUA TRIPLETT ,  MCKENNEY PAUL EDWARD

    IPC: G06F9/52 ,  G06F12/00

    CPC classification number: G06F9/52 ,  G06F9/30087

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for optimizing grace period detection following a shared data update operation that affects preemptible data readers.
    SOLUTION: A determination is made whether a data processing system is a uniprocessor system or a multiprocessor system. If the data processing system is the uniprocessor system, the grace period detection processing is performed using a first grace period detection technique. On the other hand, if the data processing system is the multiprocessor system, grace period detection processing is performed using a second grace period detection technique. The grace period detection processing determines the end of a grace period in which readers that are subject to preemption have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在影响可抢占数据读取器的共享数据更新操作之后优化宽限期检测的技术。 解决方案：确定数据处理系统是单处理器系统还是多处理器系统。 如果数据处理系统是单处理器系统，则使用第一宽限期检测技术来执行宽限期检测处理。 另一方面，如果数据处理系统是多处理器系统，则使用第二宽限期检测技术来执行宽限期检测处理。 宽限期检测处理确定宽限期的结束，其中被抢占的读者已经经过静止状态，并且不能保持对共享数据的更新前视图的引用。 版权所有（C）2010，JPO＆INPIT

    Quad aware locking primitive
    4.
    发明专利
    Quad aware locking primitive 有权
    QUAD AWARE LOCKING PRIMITIVE

    公开(公告)号：JP2007265426A

    公开(公告)日：2007-10-11

    申请号：JP2007126433

    申请日：2007-05-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F9/52 ,  G06F12/08 ,  G06F9/46 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: PROBLEM TO BE SOLVED: To handle high contention locking in a multiprocessor computer system. SOLUTION: The method organizes at least some of all the processors into a hierarchy and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. In order to ensure that the processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. The lock primitive is utilized for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：处理多处理器计算机系统中的高争用锁定。 解决方案：该方法将所有处理器中的至少一些组织到层次结构中，并响应于层次结构处理可中断锁。 该方法利用获取锁的两种替代方法，包括条件锁获取原语和无条件锁获取原语（600），以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的竞争，利用释放标志。 为了确保使用无条件锁获取原语的处理器被授予锁定，则利用切换标志。 锁原语用于基于处理器的分级位置和用于锁选择的原语来确定处理器之间的锁选择的可中断锁。 版权所有（C）2008，JPO＆INPIT

    NESTABLE READER-WRITER LOCK FOR MULTIPROCESSOR SYSTEMS
    5.
    发明申请
    NESTABLE READER-WRITER LOCK FOR MULTIPROCESSOR SYSTEMS 审中-公开
    用于多处理器系统的可编程读写器锁定

    公开(公告)号：WO0152083A3

    公开(公告)日：2002-01-03

    申请号：PCT/US0100739

    申请日：2001-01-09

    Applicant: IBM ,  MCKENNEY PAUL EDWARD

    Inventor： MCKENNEY PAUL EDWARD

    IPC: G06F15/177 ,  G06F20060101 ,  G06F9/00 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F12/06 ,  G06F15/163

    CPC classification number: G06F9/52

    Abstract: A nestable reader-writer lock minimizes writer and reader overhead by employing lock structures that are shared among groups of processors (24) that have lower latencies. In the illustrated multiprocessor system having a non-uniform memory access (NUMA) architecture, in a first embodiment each processor node has a lock structure (83) composed of a shared counter (84) and associated flag (85) for each CPU group. During a read, the counter can be changed only by processors within a CPU group performing a read. This reduced the reader overhead that otherwise would exist if all processors in the system running share a single counter. During a write, the shared flag can be changed by a process running on any processor in the system. The processors in a CPU group are notified of the write through the shared flag.

    Abstract translation: 可嵌套的读写器锁定通过使用具有较低延迟的处理器组（24）之间共享的锁结构来最小化写入器和读取器开销。 在具有不均匀存储器访问（NUMA）架构的所示多处理器系统中，在第一实施例中，每个处理器节点具有由共享计数器（84）和每个CPU组的相关标志（85）组成的锁结构（83）。 在读取期间，只能由执行读取的CPU组中的处理器更改计数器。 这减少了读取器的开销，否则将存在，如果系统中的所有处理器共享一个计数器。 在写入期间，可以通过在系统中的任何处理器上运行的进程更改共享标志。 通过共享标志通知CPU组中的处理器。

    QUAD AWARE LOCKING PRIMITIVE
    6.
    发明申请
    QUAD AWARE LOCKING PRIMITIVE 审中-公开

    公开(公告)号：WO02054175A3

    公开(公告)日：2003-01-03

    申请号：PCT/US0149529

    申请日：2001-12-28

    Applicant: IBM ,  MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy (910, 920), and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive (800) and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

    Abstract translation: 一种用于在多处理器计算机系统中有效地处理高争用锁定的方法和计算机系统。 该方法将系统中的至少一些处理器组织成层次结构（910,920），并响应于层次结构处理可中断锁定。 该方法利用获取锁的两种替代方法，包括条件锁获取原语（800）和无条件锁获取原语（600），以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的竞争，利用释放标志。 此外，为了确保使用无条件锁定获取原语的处理器被授予锁定，则利用切换标志。 因此，可以基于处理器的分层位置和用于锁选择的原语来利用锁定原语用于确定处理器之间的锁选择的可中断锁的能力来增强计算机系统的效率。

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