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    QUAD AWARE LOCKING PRIMITIVE
    1.
    发明公开
    QUAD AWARE LOCKING PRIMITIVE 审中-公开
    QUAD AWARE锁定原语

    公开(公告)号：EP1358529A4

    公开(公告)日：2008-06-04

    申请号：EP01985598

    申请日：2001-12-28

    Applicant: IBM

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F9/46 ,  G06F12/08 ,  G06F1/00 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy (910, 920), and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive (800) and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

    Quad aware locking primitive
    2.
    发明专利
    Quad aware locking primitive 有权
    QUAD AWARE LOCKING PRIMITIVE

    公开(公告)号：JP2007265426A

    公开(公告)日：2007-10-11

    申请号：JP2007126433

    申请日：2007-05-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F9/52 ,  G06F12/08 ,  G06F9/46 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: PROBLEM TO BE SOLVED: To handle high contention locking in a multiprocessor computer system. SOLUTION: The method organizes at least some of all the processors into a hierarchy and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. In order to ensure that the processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. The lock primitive is utilized for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：处理多处理器计算机系统中的高争用锁定。 解决方案：该方法将所有处理器中的至少一些组织到层次结构中，并响应于层次结构处理可中断锁。 该方法利用获取锁的两种替代方法，包括条件锁获取原语和无条件锁获取原语（600），以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的竞争，利用释放标志。 为了确保使用无条件锁获取原语的处理器被授予锁定，则利用切换标志。 锁原语用于基于处理器的分级位置和用于锁选择的原语来确定处理器之间的锁选择的可中断锁。 版权所有（C）2008，JPO＆INPIT

    QUAD AWARE LOCKING PRIMITIVE
    3.
    发明申请
    QUAD AWARE LOCKING PRIMITIVE 审中-公开

    公开(公告)号：WO02054175A3

    公开(公告)日：2003-01-03

    申请号：PCT/US0149529

    申请日：2001-12-28

    Applicant: IBM ,  MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    Inventor： MCKENNEY PAUL EDWARD ,  JACKSON BENEDICT ,  RAJAMONY RAMAKRISHNAN ,  ROCKHOLD RONALD L

    IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G06F9/52

    Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy (910, 920), and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive (800) and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

    Abstract translation: 一种用于在多处理器计算机系统中有效地处理高争用锁定的方法和计算机系统。 该方法将系统中的至少一些处理器组织成层次结构（910,920），并响应于层次结构处理可中断锁定。 该方法利用获取锁的两种替代方法，包括条件锁获取原语（800）和无条件锁获取原语（600），以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的竞争，利用释放标志。 此外，为了确保使用无条件锁定获取原语的处理器被授予锁定，则利用切换标志。 因此，可以基于处理器的分层位置和用于锁选择的原语来利用锁定原语用于确定处理器之间的锁选择的可中断锁的能力来增强计算机系统的效率。

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