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公开(公告)号：DE69022709T2
公开(公告)日：1996-05-02
申请号：DE69022709
申请日：1990-12-12
Applicant: IBM
Abstract: A computer program synchronization instruction is employed to synchronize multiple processing devices (18,20,22) sharing main storage (38) through a common interface (36). The processors execute the synchronization instruction in turn, and all except the final processor are forced into a temporary holdoff condition and execute no further computer program instructions. The final processor to execute the synchronization program becomes a master, releasing itself and the "slave" devices simultaneously to resume executing instructions. In order to force contentions between processors, a selected delay may be entered into the instruction stream of at least one of the processing devices. The delay can be incremented each time the synchronization instruction is executed, if desired. The forced contentions permit a testing of various serialization mechanisms designed to resolve contentions.
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公开(公告)号：DE3586227D1
公开(公告)日：1992-07-23
申请号：DE3586227
申请日：1985-08-20
Applicant: IBM
Inventor： LEWIS DAVID O , MCMAHON LYNN ALLEN , SCHARDT TERRY L
Abstract: A look-aside buffer in a computer system has a memory containing at least a first type of data and a second type of data stored in a page format. The look-aside buffer is arranged to retain at least two different real addresses as resolved by the system which indicate pages containing the different types of data. One of the addresses is indicated as least recently used by a marker and such address is deleted when a further different address is resolved by the system unless the address being resolved is an address corresponding to the first type of data. In such a case, the marker is not changed such that the second type of data addresses are not deleted from the look-aside buffer as a result of resolution of a first type data page address by the system.
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公开(公告)号：DE69022709D1
公开(公告)日：1995-11-02
申请号：DE69022709
申请日：1990-12-12
Applicant: IBM
Abstract: A computer program synchronization instruction is employed to synchronize multiple processing devices (18,20,22) sharing main storage (38) through a common interface (36). The processors execute the synchronization instruction in turn, and all except the final processor are forced into a temporary holdoff condition and execute no further computer program instructions. The final processor to execute the synchronization program becomes a master, releasing itself and the "slave" devices simultaneously to resume executing instructions. In order to force contentions between processors, a selected delay may be entered into the instruction stream of at least one of the processing devices. The delay can be incremented each time the synchronization instruction is executed, if desired. The forced contentions permit a testing of various serialization mechanisms designed to resolve contentions.
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