公开(公告)号：GB988085A

公开(公告)日：1965-04-07

申请号：GB557261

申请日：1961-02-15

Applicant: IBM

Inventor： OWEN CHARLES EDWARD ,  METCALFE HARRY FRANCIS ,  MEGGITT JOHN EDWARD

IPC: G06F9/26

Abstract: 988,085. Programming arrangements for computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 15, 1962 [Feb. 15, 1961], No. 5572/61. Drawings to Specification. Heading G4A. In a digital electric calculator which comprises a number of registers each operable under the control of timing impulses to receive data on a set of common drive lines and to make data available on a set of common sense lines at predetermined times in the cycle of operation, the selected lines of the set of sense lines are shared by a control matrix itself operable under control of the timing impulses to deliver data to the sense lines, and the latter are connected to temporary storage means operable to transfer information carried by the sense lines to the drive lines. The invention is primarily concerned with microprogramming. A microprogram usually consists of the sense lines threading a column of cores of the control matrix, and it is necessary to increment only a so-called y-address at each step of the microprogram to select the next control core. This is done automatically by the means described in Specification 981,780. Changing the x-address requires a special micro-order. A description is given of the operation of the control system in a small digital computor having a keyboard data entry, and a typewriter for program tape input and for output. The arithmetic unit consists of a subtractor matrix working to radix 12. There is a main core store having yaddress registers A, B, a working store having y-address registers, P, Q together with single respective x-address registers, an arithmetic register T and a set of condition cores an appropriate one of which is set when a specific condition (negative signa, over flow &c. exists. The P.Q. registers are also arithmetic registers. There is described in some detail with reference to Figs. 1 to 6 (not shown) a 21-point operating cycle for each microinstruction in which the following operations are carried out: 1. Store to register, or register to store,transfer. 2. Subtract P or Q from arithmetic register T. Result to T. 3. Load constant into P or Q. 4. Select next microinstruction, with or without conditional branching. The subtraction matrix consists of an array of magnetic cores the row and column selection lines representing the operands and sense lines threading those cores at the intersection of selection lines representing numbers having the same difference (Fig. 7 not shown). A microprogram is initiated from the input program tape which carries the address of the first control core.

公开(公告)号：GB1014391A

公开(公告)日：1965-12-22

申请号：GB3372161

申请日：1961-09-20

Applicant: IBM

Inventor： MEGGITT JOHN EDWARD

IPC: G06F7/48 ,  G06F7/498

Abstract: 1,014,391. Electronic calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 19, 1962 [Sept. 20, 1961], No. 33721/61. Heading G4A. The Specification describes operations called pseudo - multiplication and pseudo - division. These are similar to division by repeated subtraction and multiplication by repeated addition save that the subtrahend or addend are modified as the computation proceeds. Among other examples the Specification describes the computation of log (1 + y/x). Digits q; are found by pseudo-division such that y + x x = x# (1 + 10 -j )qj . . . . . (1) j = o Then log(1 + y/x) = # j qj log(1 + 10 -j ) . . . (2) The process by which the RH side of (2) is evaluated is termed pseudo-multiplication. Ordinary division is defined by the equations, referring to the computation of the jth order of the quotient, qj, y n +1 = yn - 10 j x n . . . . . . (3) x n + 1 = x n . . . . . . . . . . . (4) For accuracy it is usual for the dividend register to be shifted rather than the divisor registe and so, putting 10 -j yn = Z n , (3) becomes Zn + 1 = z n - x n . . . . . (5) Then, qj is defined by Zq j # o > Zqj + 1 Pseudo division differs from this only in the equation (4). It is shown in the Specification that the computation of the qj of (1) is defined by equations (5), (6) and X n + 1 = X n + 10 -j x n The apparatus used is shown in Fig. 1. There are three operand registers, A and M of one full word length, and B of one word length plus two digits. An adder 3 has as inputs A or B in true form and B or M in true or complement form. The output is connected to all three registers and an indication of carry or borrow from the highest order is given. There is an operations counter 7 and a control unit 1 of the microprogram type, which stores control words of which the individual bits each control a specific gate. The control unit also generates the address in the unit of the next control word, which address may be modified by the signal on line 8. The Specification states that the adder 3 may be in the form of a stored table. A flow sheet for the operation of the apparatus in performing ordinary division (y/x) and pseudo-division in evaluating log (1 + y/x), tan -1 (y/x) and (y/x)¢ is shown in Figure 2a. The Specification describes how the inverse functions (squares, exponentials, trigonometric functions) can be calculated using a similar process and states that a combined register for operand and result data may be provided.

公开(公告)号：GB975979A

公开(公告)日：1964-11-25

申请号：GB1959162

申请日：1962-05-22

Applicant: IBM WORLD TRADE LAB GREAT BRIT

Inventor： MEGGITT JOHN EDWARD ,  HERBERT JOHN RICHARD ,  SHARP JOHN JOSHUA

IPC: G11B5/52 ,  G11B19/20

Abstract: 975,979. Disc record data storage apparatus. IBM WORLD TRADE LABORATORIES (GREAT BRITAIN) Ltd. Jan. 10, 1963 [May 22, 1962], No. 19591/62. Heading G5R. Arcuate tracks 64 Fig. 3 on a magnetic disc 12 are scanned by rotating the disc and a head 60 about axes 16, 44 respectively the head being maintained in constant orientation with its track on the axis 62 by gears 52, 54, 56 in the inverse direction to the relative rotation of transducer and disc along the track. The head is only operational for 120 degrees of each successive track circuit to avoid overlapping, and improved track packing-density may be achieved near the centre of the disc, Fig. 4 by varying the start of the operational sector. In an alternative embodiment, Fig. 5, the head is aligned, not by rotation about the axis 62 (Fig. 1) but by a parallel-linkage movement. The precession of the tracks by incremental rotation of a gear coupled to a differential 26, or by a stepping motor included between 24 and 38, is claimed in Specification 975,978. Multiple head-driving arrangements may be used. A single head may be precessed by making the drive ratios for head and disc slightly different from unity.

公开(公告)号：GB975978A

公开(公告)日：1964-11-25

申请号：GB1959062

申请日：1962-05-22

Applicant: IBM WORLD TRADE LAB GREAT BRIT

Inventor： MEGGITT JOHN EDWARD ,  HERBERT JOHN RICHARD ,  SHARP JOHN JOSHUA

IPC: G11B5/52 ,  G11B19/20

Abstract: 975,978. Disc record data storage apparatus. IBM WORLD TRADE LABORATORIES (GREAT BRITAIN) Ltd. Jan. 10, 1963 [May 22, 1962], No. 19590/62. Heading G5R The description of Figs. 1-5 is the same as in Specification 975, 979, but the claims are directed to the means for incrementally processing successive tracks. The description extends to multi-head embodiments providing continuous recording:- Fig. 6 requires slip-rings for the heads, but only one drive means for the heads; Figs. 7 and 8 require three drive means but no slip rings since the partial tracks do not overlap. Fig. 9 is equivalent to the single-head embodiment in Fig. 5 (not shown, but see Specification 975,979). Stacked assemblies of discs with relevant heads and common drive means may be used, particularly where the information on the discs is related in decade manner. The heads are preferably of the type supported over the discs by Bernonilli effect.