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公开(公告)号：DE2442772A1
公开(公告)日：1975-03-13
申请号：DE2442772
申请日：1974-09-06
Applicant: IBM
Inventor： OWEN CHARLES EDWARD , TAUB DANIEL MATTHEW
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公开(公告)号：DE2642205A1
公开(公告)日：1977-03-31
申请号：DE2642205
申请日：1976-09-20
Applicant: IBM
Inventor： BARCLAY DONALD JOHN , BIRD COLIN LEONARD , HALLETT MICHAEL HENRY , MINSHULL JOHN FRANCIS , OWEN CHARLES EDWARD , KIRKMAN DAVID HORROBIN
Abstract: 1473772 Controlling light INTERNATIONAL BUSINESS MACHINES CORP 30 Sept 1975 39872/75 Heading G2F [Also in Division G5] In a display device comprising a transfer electrode El, a dump electrode E2 and a plurality of display electrode E3 immersed in a liquid electrolyte, a potential difference is first applied between electrodes E1 and E2 such as to deposit coloured material on E1, and subsequently a potential difference is applied between E1 and at least one electrode E3 so as effectively to transfer the coloured material to the selected electrode(s) E3. In Fig. 2, dot electrodes E3 are arranged in rows and columns, each column having a respective electrode E1 and E2 and the electrolyte being separated from that in adjacent columns by partitions 14 or by being contained in channels in a substrate. If the coloured material is such as to deposit at a cathode, it is initially deposited on selected electrode E1 by earthing the conductor 15 (FET 18, input T2) and by turning on selected FETs 19 to render corresponding electrode E2 positive. FETs 19 are controlled by a like array of bi-stables 23 forming an input/output register 24, AND gate 22 and control input Cl applied simultaneously with input T2. Subsequently an input T1 renders conductor 15 positive and, in the previously selected columns only, the coloured material is effectively transferred to the electrodes E3 of a selected row by activating the corresponding row input R2 (row conductor to earth). By repeating the process the array is scanned row sequentially. Non-linear resistances Z, e.g. oppositely poled diodes connected in parallel, are preferably provided between each electrode E1 and E3 and its row conductor. Erasure of the display is by turning on FETs 21 (input C2) and successively energizing terminals R1, or by short-circuiting the electrodes E3 to the dump electrode E2. The former erasure method may be used when the display requires refreshing to overcome dissipation of the coloured material by diffusion effects. The current between an electrode E2 and a coloured electrode E3 causes a current sense amplifier 27 to set the respective bi-stable 23 for a subsequent re-writing step. Partial or complete erasure of the display due to electrical read-out thereof may be counteracted similarly by applying sequential positive and negative current pulses across electrodes E2 and E3, the nett current being zero. During the positive pulse, terminal 29 is energized and the current between a written electrode and the electrode E2 produces an output from the amplifier 27, so that the following negative pulse restores the electrode E3 to its original written state. The device may also be constructed as a seven segment display.
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公开(公告)号：DE1282331B
公开(公告)日：1968-11-07
申请号：DEJ0021218
申请日：1962-01-26
Applicant: IBM
Inventor： OWEN CHARLES EDWARD , PROUDMAN ANTHONY , HUFFELL JOHN GEORGE WILLIAM
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Patent Agency Ranking
公开(公告)号：DE1198090B
公开(公告)日：1965-08-05
申请号：DEJ0020361
申请日：1961-08-05
Applicant: IBM
Inventor： TAUB DANIEL MATTHEW , PEACOCK ANTONY , OWEN CHARLES EDWARD
IPC: G06F9/26
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公开(公告)号：GB988085A
公开(公告)日：1965-04-07
申请号：GB557261
申请日：1961-02-15
Applicant: IBM
Inventor： OWEN CHARLES EDWARD , METCALFE HARRY FRANCIS , MEGGITT JOHN EDWARD
IPC: G06F9/26
Abstract: 988,085. Programming arrangements for computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 15, 1962 [Feb. 15, 1961], No. 5572/61. Drawings to Specification. Heading G4A. In a digital electric calculator which comprises a number of registers each operable under the control of timing impulses to receive data on a set of common drive lines and to make data available on a set of common sense lines at predetermined times in the cycle of operation, the selected lines of the set of sense lines are shared by a control matrix itself operable under control of the timing impulses to deliver data to the sense lines, and the latter are connected to temporary storage means operable to transfer information carried by the sense lines to the drive lines. The invention is primarily concerned with microprogramming. A microprogram usually consists of the sense lines threading a column of cores of the control matrix, and it is necessary to increment only a so-called y-address at each step of the microprogram to select the next control core. This is done automatically by the means described in Specification 981,780. Changing the x-address requires a special micro-order. A description is given of the operation of the control system in a small digital computor having a keyboard data entry, and a typewriter for program tape input and for output. The arithmetic unit consists of a subtractor matrix working to radix 12. There is a main core store having yaddress registers A, B, a working store having y-address registers, P, Q together with single respective x-address registers, an arithmetic register T and a set of condition cores an appropriate one of which is set when a specific condition (negative signa, over flow &c. exists. The P.Q. registers are also arithmetic registers. There is described in some detail with reference to Figs. 1 to 6 (not shown) a 21-point operating cycle for each microinstruction in which the following operations are carried out: 1. Store to register, or register to store,transfer. 2. Subtract P or Q from arithmetic register T. Result to T. 3. Load constant into P or Q. 4. Select next microinstruction, with or without conditional branching. The subtraction matrix consists of an array of magnetic cores the row and column selection lines representing the operands and sense lines threading those cores at the intersection of selection lines representing numbers having the same difference (Fig. 7 not shown). A microprogram is initiated from the input program tape which carries the address of the first control core.
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公开(公告)号：GB981780A
公开(公告)日：1965-01-27
申请号：GB2131460
申请日：1960-06-17
Applicant: IBM
Inventor： OWEN CHARLES EDWARD
IPC: G11C11/06
Abstract: 981,780. Digital data storage; microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 12, 1961 [June 17, 1960], No. 21314/60. Headings G4A and G4C. On selecting an address in a storage matrix 1 of magnetic cores the next address is set up in a selection register. Register 2 selects a column of matrix 1 and the column wires are threaded through the cores of the selection register 2 so as to set the cores A 1 to A 5 to represent the column selected less one, the cores B 1 to B 8 to represent the same column, and the cores C 1 to C 8 to represent the column selected plus one, as illustrated for the fifth column. The outputs of the cores are gated by a strobe signal on line 9 to a decoder 10 which marks one out of sixteen lines. The cores in each row of the register take values according to the 1, 2, 4, 8 code. To select a column of the matrix 1, one of the transistor switches 6 is closed and a full read pulse is given to all the cores of register 2 by means of winding 4, together with a half-write pulse on winding 5a which is effective only on that row of the register associated with the closed switch 6. The effect is that two of the rows of register 2 are cleared. The pulse on winding 5a stops and a strobe pulse issues, permitting the setting of the uncleared row to be read to decoder 10 and selecting one of the column lines of matrix 1. The marking of the column line causes all three rows of the register to be set. A switch 6 is then closed, perhaps according to the information read from matrix 1, and the process repeated. The invention is applied to microprogramming in which a microinstruction contains the address of the next microinstruction.
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公开(公告)号：GB1299530A
公开(公告)日：1972-12-13
申请号：GB4474770
申请日：1970-09-19
Applicant: IBM
Inventor： OWEN CHARLES EDWARD
IPC: H04L25/49
Abstract: 1299530 Data storage INTERNATIONAL BUSINESS MACHINES CORP 19 Sept 1970 44747/70 Heading G4C [Also in Division H3] A decoding circuit for decoding a train of input pulses, the pulses being spaced from each other by one of two nominal intervals, uses each pulse to cause flyback in a sawtooth, an output being produced whenever the sawtooth passes a threshold, the flyback having one of two different magnitudes according to the presence or absence of an output, these magnitudes being fixed so that displacement of an input pulse from its nominal position dces not effect the time at which the succeeding ramp either reaches or, but for an intervening flyback, would have reached the threshold. In Fig 1, the input 1 has a long interval between consecutive pulses to represent "1" and two-thirds this interval to represent "0" The sawtooth generator is basically a Miller integrator, with controlling capacitor 3 and Darlington pair 4, 5. Each ramp is produced by discharge of 3 via resistors 6, 7 and transistor 8. When the (negative-going) ramp goes below a threshold E, a long-tailed comparator 18, 19 sets a trigger 2 to produce an output T indicating "1" A capacitor 9 normally charges via resistors 13, 14, but each input pulse at 1 reduces the charging voltage by enabling transistor 11 to provide a shunt of resistance depending on the presence or absence of T at transistor 12. The reduction in charging voltage for capacitor 9 charges capacitor 3 (flyback). The ramp slope is varied to compensate for long-term frequency variations (due to speed variation in the drum or disc from which input 1 comes) by using the level on a capacitor 21 via a low-pass filter 22 to control the resistance of the discharge path 6, 7, 8 of ramp capacitor 3, at transistor 8. While the sawtcoth is above a reference level defined by a potentiometer 23, as determined by a long-tailed comparator 24, 25, capacitor 21 is charged via a transistor 26 (except that in the case of a preceding "0" bit, half the current is diverted via a transistor 27 due to the control of a transistor 29 by trigger 2, to provide for the fact that the sawtcoth is below the reference level for twice as long for a "1" as for a "0"). While the sawtooth is below this reference level, capacitor 21 discharges via transistor 27, so that in the absence of frequency variations, the average level on capacitor 21 is zero. Non- ideal flyback can be compensated for by a capacitor (short time constant) connected between transistor 11 collector and transistor 24 base. Synchronization of the circuit is achieved by an initial block of zerces followed by a block of ones. The invention can be applied to double-frequency encoded input (having regular clock pulses, a data pulse being present or absent half way between consecutive clock pulses for "1" and "0" respectively, viz. long interval for "0", two short intervals for "1") by subtracting the long interval indicating signal from the input signal and dividing the remainder by two to get pulses indicating "1"s. Decoding of address marks represented by omission of the clock pulses can also be done using suitable logic.
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公开(公告)号：GB1126160A
公开(公告)日：1968-09-05
申请号：GB3936967
申请日：1967-08-26
Applicant: IBM
Inventor： OWEN CHARLES EDWARD , WALLIS CHRISTOPHER NORMAN
Abstract: 1,126,160. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 26 Aug., 1967, No. 39369/67. Heading G4C. [Also in Division H3] A circuit for selecting regularly recurring pulses e.g. from a magnetic disc store comprises a gate and a ramp generator, the pulses providing one input to the gate and the other input being provided by the ramp when it exceeds a controlled value, the flyback of the ramp having a constant amplitude irrespective of ramp length and being initiated by the output of the gate. As applied to a magnetic disc store, binary data D (Fig. 2a) is represented by the presence and absence of a pulse between succesive clock pulses C. The data pulses cause the recorded clock pulses to be pushed apart, as shown dotted, but as the flyback is of constant amplitude the point at which the ramp (Fig. 2b) crosses the threshold T of the gating circuit is not affected. The input pulse train 2(a) alternatively may be derived (Figs. 3a-3g, not shown) from a signal (Fig. 3a) in which a change of binary data between its two values is represented by a change of phase of the signal. The signal is differentiated (3c) squared (3d) and produces pulses at the resulting leading and trailing edges (3c and f). These are combined to form the derived train (3g). Circuit details (Fig. 1).-The input pulses (2a) are applied at 13 to gate 14. The output pulses of the gate discharge capacitor 18 through diode 19 and the trailing edge transfers the charge to a Miller capacitor 21 to produce a determined magnitude of flyback. Capacitor 21 then discharges linearly to produce a ramp voltage (2b) at the input of transistor 32. The input of this transistor comprises a circuit which biases it to allow a predetermined portion of the end of the ramp to pass through transistors 32 and 37 to produce pulses 2(c) which are applied to the other input of gate 14 and thus to allow the next clock pulse to pass. The output from 32 is also applied to a gate 15 to block the clock pulses and allow the data to pass. An averaging circuit 26 1 , 27 controls the rate of discharging of the Miller capacitor 21 so as to stabilize the amplitude of the sawtooth wave.
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