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    AUTOMATIC PATH REARRANGEMENT FOR BLOCKING SWITCHING MATRIX
    6.
    发明专利
    AUTOMATIC PATH REARRANGEMENT FOR BLOCKING SWITCHING MATRIX 未知

    公开(公告)号：CA1176358A

    公开(公告)日：1984-10-16

    申请号：CA407333

    申请日：1982-07-15

    Applicant: IBM

    Inventor： MELAS CONSTANTIN M

    IPC: H04Q3/545 ,  H04Q3/52 ,  H04Q3/64 ,  H04Q3/68

    Abstract: AUTOMATIC PATH REARRANGEMENT FOR BLOCKING SWITCHING MATRIX A method is described for rearranging signal paths in a three stage (primary, intermediate, tertiary) switching network to permit data or digitized voice signals to be transmitted from any given primary outlet to any given tertiary inlet. The intermediate stage has fewer inlets than the number of primary stage outlets and fewer outlets than the number of tertiary stage inlets, making the network a conditionally blocking one. Two call rearranging buses are provided to assure that each signal path being rearranged is maintained to prevent data transmission drop outs. Primary to intermediate and intermediate to tertiary paths are rearranged one at a time using the call rearranging buses to "move" free primary and tertiary links to a single intermediate matrix. RA9-79-011

    DIGITAL SPACE DIVISION EXCHANGE
    7.
    发明专利
    DIGITAL SPACE DIVISION EXCHANGE 未知

    公开(公告)号：CA1176359A

    公开(公告)日：1984-10-16

    申请号：CA407323

    申请日：1982-07-15

    Applicant: IBM

    Inventor： MELAS CONSTANTIN M ,  PATTEN MICHAEL A

    IPC: H04Q3/545 ,  H04Q3/68 ,  H04Q3/54

    Abstract: DIGITAL SPACE DIVISION EXCHANGE A switching network is comprised of a plurality of identical chips and a network (control) processor. Each of the chips is a novel intelligent switch and includes both a cross point array as well as apparatus to control the cross point array in response to a set of multi bit commands or to formulate a response to a query concerning status of the switching array. The number of command lines connecting network (control) processor to each of the array chips may be as few as two. The cross point array includes a cross point device (switch) for each inlet-outlet combination. The total number of cross points in the network is lower than that dictated by a CLOS network.

    8.
    发明专利
    未知

    公开(公告)号：DE1127117B

    公开(公告)日：1962-04-05

    申请号：DEJ0018338

    申请日：1960-06-25

    Applicant: IBM

    Inventor： MELAS CONSTANTIN M

    IPC: G11B20/14 ,  H03K5/05 ,  H04L7/02 ,  H04L7/027 ,  H04L25/49

    Abstract: 902,450. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 1, 1960 [July 1, 1959], No. 23073/60. Class 40 (3). [Also in Group XL (c)] The invention provides a self-clocking system for binary data signals, particularly for signals subject to jitter distortion, and includes means for rephasing the clock signal relative to the incoming data signal at each transition in the latter. General operation, Fig. 1.-Data signals from a source 17 pass to a clamping-pulse generator 12 and to a sampling circuit 13. The generator 12 feeds a clamp 11 which controls the phasing of a free-running multivibrator 10. The out-. put of the sampling circuit is thereby clocked with reference to the multivibrator output. Detailed operation.-In the clamping pulse generator and clamp, Fig. 5, binary signals such as DS, Fig. 2, pass direct to one input of an OR circuit 18 and via a half-bit delay 19 to the other input. The OR circuit output is inverted, line 4, Fig. 2, and passed to the clamp circuit 11. The output of the clamp 11 is employed to vary the phase of the multivibrator 10, Fig. 1, the multivibrator output-the clocking signalbeing as in line MV, Fig. 2. Fig. 6 shows an alternative circuit of the pulse generator and clamp, the generator comprising a phase inverter 27 which feeds two mono-stable triggers 26, 27. These triggers generate clamping pulses having a length determined by the discharge rates of capacitors 28, 28 1 . Transistor 29 acts as the clamp. The sampling circuit, Fig. 7, comprises AND circuits 31, 32, a bi-stable trigger 34 and an inverter 33. The trigger output is the clocked data, line 6, Fig. 2, resulting from the inputs of clock pulses MV and data signals DS. Trigger 34 is triggered only by negative-going pulses.

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