公开(公告)号：DE3382307D1

公开(公告)日：1991-07-11

申请号：DE3382307

申请日：1983-12-22

Applicant: IBM

Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK ,  RADIN GEORGE

IPC: G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14

Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.