公开(公告)号：JPH04247528A

公开(公告)日：1992-09-03

申请号：JP25287591

申请日：1991-09-05

Applicant: IBM

Inventor： DEBITSUDO POURU BURERUSUFUOODO ,  MERUBIN EMU KATORAA ,  JIIN RUISU RAFUITSUTE ,  JIYOSEFU MAATEIN GUDANIETSUKU ,  DAMIAN REO OSHISETSUKU ,  KENESU AANESUTO PURAMUBETSUKU

IPC: G06F9/46 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: PURPOSE: To access an address space of which multiple host access register is specified without executing guest dynamic address translation and guest access register translation. CONSTITUTION: In a host access register mode, a field B of a guest instruction specifies an access register 16 including an ALET. In the case of translating the ALET by a host ART 10, a host STD is applied to an address space for storing data. The host STD 19 applied from the host ART 10 is combined with a host virtual address applied from an adder 15, the combined data are converted by a host dynamic translator(HDT) 18 to obtain a host real address of an operand.