公开(公告)号：JPH0683710A

公开(公告)日：1994-03-25

申请号：JP691593

申请日：1993-01-19

Applicant: IBM

Inventor： KAARU EDOWAADO KURAAKU ,  JIEFUREI ARAN FUREI ,  KENESU AANESUTO PURAMUBETSUKU ,  KIYASUPAA ANSONII SUKARUZUI ,  BAASUKAA SHINHA

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46

Abstract: PURPOSE: To provide an efficient inter-space branch process to separated programs in different address spaces in a group of related address spaces of a subsystem. CONSTITUTION: The group has a fundamental space and at least one partial space, and each partial space can include a program and data, which cannot be accessed from other partial spaces, to separate the program and data in a subsystem. Any CPU in a computer system can designate programs found in address spaces. A designating process checks authority for access to the group of a user of the group and executes an intra-group program call instruction which designates first and second general registers.

公开(公告)号：JPH01228038A

公开(公告)日：1989-09-12

申请号：JP31965988

申请日：1988-12-20

Applicant: IBM

Inventor： RICHIYAADO IIUIN BAAMU ,  TERII RII BOODEN ,  JIYASUTEIN RARUFU BATSUTOUERU ,  KAARU EDOWAADO KURAAKU ,  AREN JIYOOJI GANEKU ,  JIEEMUZU RAMU ,  MAIKERU JIERAADO MAARU ,  KENESU AANESUTO PURAMUBETSUKU ,  KIYASUPAA ANSONII SUKARUZUI ,  RICHIYAADO JIYON SHIYAMARUZU ,  RONARUDO MOOTON SUMISU ,  JIYURIAN TOOMASU

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/14

Abstract: PURPOSE: To block undesired access to an address space by performing the user management of address space corresponding to a token applied from a system for space identification. CONSTITUTION: An access register transform(ART) operation 10 uses contents in an access register for providing a segment table describer(STD) to be used for dynamic address translation(DAT). An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. The STD from the ART 10 is combined with the logical address from the adder 15 and translated together by a DAT 18, and the real address of an operand to be used for the system is generated.

公开(公告)号：JPH04247528A

公开(公告)日：1992-09-03

申请号：JP25287591

申请日：1991-09-05

Applicant: IBM

Inventor： DEBITSUDO POURU BURERUSUFUOODO ,  MERUBIN EMU KATORAA ,  JIIN RUISU RAFUITSUTE ,  JIYOSEFU MAATEIN GUDANIETSUKU ,  DAMIAN REO OSHISETSUKU ,  KENESU AANESUTO PURAMUBETSUKU

IPC: G06F9/46 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: PURPOSE: To access an address space of which multiple host access register is specified without executing guest dynamic address translation and guest access register translation. CONSTITUTION: In a host access register mode, a field B of a guest instruction specifies an access register 16 including an ALET. In the case of translating the ALET by a host ART 10, a host STD is applied to an address space for storing data. The host STD 19 applied from the host ART 10 is combined with a host virtual address applied from an adder 15, the combined data are converted by a host dynamic translator(HDT) 18 to obtain a host real address of an operand.

公开(公告)号：JPH01228039A

公开(公告)日：1989-09-12

申请号：JP31966488

申请日：1988-12-20

Applicant: IBM

Inventor： RICHIYAADO IIUIN BAAMU ,  TERII RII BOODEN ,  JIYASUTEIN RARUFU BATSUTOUERU ,  KAARU EDOWAADO KURAAKU ,  AREN JIYOOJI GANEKU ,  JIEEMUZU RAMU ,  MAIKERU JIERAADO MAARU ,  DEBUIDO RICHIYAADO PEEJI ,  KENESU AANESUTO PURAMUBETSUKU ,  KIYASUPAA ANSONII SUKARUZUI ,  RICHIYAADO JIYON SHIYAMARUZU

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

Abstract: PURPOSE: To make permission hierarchical and non-hierarchical as well by providing a program permitting mechanism equipped with plural access registers and an access register transformation(ART) means. CONSTITUTION: An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. An ART operation 10 uses contents in access registers 16 for providing a segment table describer (STD) to be used for dynamic address translation(DAT). When an access list entry token (AELT) is transformed by the ART 10, the STD corresponding to an address space for storing data is applied. The real address of an operand to be used for a system is generated from DAT 18.