公开(公告)号：JP2002082844A

公开(公告)日：2002-03-22

申请号：JP2001185487

申请日：2001-06-19

Applicant: IBM

Inventor： LINAM STEPHEN DALE ,  MICHAEL ANTHONY PERES ,  LOUIS GABRIEL RODRIGUEZ ,  MARK WALTZ WENING

IPC: G06F13/14 ,  G06F20060101 ,  G06F3/00 ,  G06F11/00 ,  G06F11/267 ,  G06F11/34 ,  G06F13/00

Abstract: PROBLEM TO BE SOLVED: To provide a method, a system and a device for managing a failed input-output adapter in a data processing system. SOLUTION: An operating system handler receives an instruction that one of a plurality of input-output adapters fails. The operating system handler checks an error log to decide which input-output adapter fails. When the operating system handier decides the failed input-output adapter, the handler disables the failed input-output adapter without powering down the data processing system and releases all pieces of allocated processing going to the failed input- output adapter. Next, a user is notified of the failed input-output adapter so that the user can replace the failed input-output adapter. The input-output adapter can be replaced with a new input-output adapter without powering down the data processing system. When the failed input-output adapter is replaced, the new input-output adapter is enabled.

公开(公告)号：JP2002175268A

公开(公告)日：2002-06-21

申请号：JP2001298359

申请日：2001-09-27

Applicant: IBM

Inventor： MICHAEL ANTHONY PERES

IPC: G06F12/08 ,  G06F13/20 ,  G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide a method, a system and a device for supplying an input/ output adapter with data from a PCI-PCI bus bridge. SOLUTION: In one embodiment, when the PCI-PCI bus bridge receives a request of data from the input/output adapter, the PCI-PCI bus bridge determines whether the requested data are included in a cache memory in the bridge or not, and, when included, supplies the input/output adapter with the data. When not included, first of all, the bridge caches the data from a system memory. In order to guarantee that the data in the cache memory are not old, a signal for showing whether data in a buffer are old or not is supplied periodically or aperiodically from a PCI host bridge to the PCI-PCI bridge. When the data are old, in some embodiments, the contents in all the buffers are cleared, and, in other embodiments, only the contents in the buffers including old data are cleared.

公开(公告)号：JP2008287718A

公开(公告)日：2008-11-27

申请号：JP2008125889

申请日：2008-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MICHAEL ANTHONY PERES ,  PAYNTON CALVIN CHARLES ,  KENDALL KRIS MARIE

IPC: G06F13/10

CPC classification number: G06F13/4273

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for dynamically reassigning buffer space to maximize I/O performance of virtual lanes.
SOLUTION: The system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassigns the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于动态重新分配缓冲区空间以最大化虚拟通道的I / O性能的系统和方法。 解决方案：用于动态重新分配缓冲空间的系统和方法从未使用的虚拟通道中获取缓冲区空间，并在IO配置发生更改时将未使用的缓冲区重新分配给已使用的虚拟通道。 例如，在支持仅有两个虚拟通道正在使用的四个虚拟通道的实施例中，该系统和方法从另外两个未使用的虚拟通道重新分配缓冲区空间，供使用中的两个虚拟通道使用。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH10307791A

公开(公告)日：1998-11-17

申请号：JP8476598

申请日：1998-03-30

Applicant: IBM

Inventor： SCOTT LEONARD DANIEL ,  MICHAEL ANTHONY PERES ,  PAUL GORDON ROBERTSON ,  JOHN DANIEL UPTON

IPC: G06F11/30 ,  G06F13/362

Abstract: PROBLEM TO BE SOLVED: To optimize the performance of a bus in real time without any user's intervention by monitoring and analyzing the performance of the bus, and controlling some of performance parameters in response to the analysis result. SOLUTION: The method 10 for optimizing the bus performance initializes the bus at its start (step 102). Then the bus performance is monitored (step 104). Information obtained by monitoring the performance is used for an analysis (step 106). Then bus parameters are altered so as to take correction measures and optimize the performance (step 108). Further, manually specified alterations can be made (step 110). Consequently, a user limits control over the parameters or sets parameters and then the performance of the bus can be prevented from dynamically be corrected by the method 100.

公开(公告)号：JP2008287717A

公开(公告)日：2008-11-27

申请号：JP2008125760

申请日：2008-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MICHAEL ANTHONY PERES ,  PAYNTON CALVIN CHARLES ,  KENDALL KRIS MARIE

IPC: G06F13/38

CPC classification number: G06F13/4045 ,  H04L49/90

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for reassigning buffer space to maximize IO performance of virtual lanes. SOLUTION: This system and method takes the buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassigns the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供重新分配缓冲区空间以最大化虚拟通道的IO性能的系统和方法。 解决方案：该系统和方法从未使用的虚拟通道获取缓冲区空间，并将未使用的缓冲区重新分配到使用的虚拟通道。 例如，在支持仅有两个虚拟通道正在使用的四个虚拟通道的实施例中，该系统和方法从另外两个未使用的虚拟通道重新分配缓冲区空间，供使用中的两个虚拟通道使用。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002342178A

公开(公告)日：2002-11-29

申请号：JP2002078872

申请日：2002-03-20

Applicant: IBM

Inventor： AUSTEN CHRISTOPHER HARRY ,  MICHAEL ANTHONY PERES ,  MARK WALTZ WENING

IPC: G06F13/00 ,  G06F11/00 ,  G06F11/07 ,  G06F11/267 ,  H04B1/74

Abstract: PROBLEM TO BE SOLVED: To provide a method for fixing a priority order to a bus error of a computer system. SOLUTION: A subsystem test is performed on a first subsystem from a plurality of subsystems on a bus system, and the subsystem test on the bus system is inherent to a first bus subsystem. An output is received in response to the performance of the subsystem test. A significance level is evaluated on the basis of an error in response to an output showing the error in the first subsystem. A subsystem test is performed for each of the remaining subsystems about the entire subsystems from the plurality of subsystems on the bus system, and each subsystem test on the bus system is inherent to each of the remaining subsystems. An output is received in response to the performance of each subsystem test. A significance level is evaluated on the basis of an error in response to an output showing the error in any of the remaining subsystems.