公开(公告)号：JPH10188565A

公开(公告)日：1998-07-21

申请号：JP33033797

申请日：1997-12-01

Applicant: IBM

Inventor： MICHAEL K SHIRAURA ,  LATTIMORE GEORGE M ,  GASS WAI-YANG YUNG

IPC: G11C11/41 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM structure capable of reducing the power consumption by conditionally restoring only a memory cell to be evaluated. SOLUTION: A device has arbitrary number of memory cells 72, multiple word lines 76, and multiple predecoded address lines 78 and 80, which enable to select one line from the multiple word lines 76. The memory cells 72 are arrayed in a group 74, and each group has a connected bit line. A precharge circuit is connected to the bit line to restore a specified cell of the memory cells 72, after the evaluating operation. The predecoded address lines 78 and 80 provide encoded information concerning the address related to the evaluated memory cells 72, and a decoder identifies the address to determine which word line to use for accessing the evaluated memory cells 72.

公开(公告)号：JPH1093411A

公开(公告)日：1998-04-10

申请号：JP18143197

申请日：1997-07-07

Applicant: IBM

Inventor： MICHAEL K SHIRAURA ,  CHUN WAI RAU ,  GEORGE M RATEIMOA ,  GAS W JUNG

IPC: H03K19/003 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To prevent an output error by connecting a delay element between an output node and a recharging transistor to increase recharging time to reduce the sensitivity of dynamic circuit to alpha particles and cosmic rays causing early discharge. SOLUTION: A delay element 134 is connected between the output node 132 and the recharging control input 123 of the recharging transistor 122. Thereby the element 134 increases time for recharging an active node 118 by the transistor 122. Thereby the sensitivity of the dynamic circuit 110 to alpha particles, cosmic rays and other particles generating causing early discharge is deteriorated to prevent the output error of the output node 132. In addition the delay element 134 introduces additional resistance to increase the capacitance of the output node 132 and a time constant generated between the output node 132 and the recharging control input 123. The recharging time of the transistor 122 is extended by the increase this time constant.