公开(公告)号：GB2532210A

公开(公告)日：2016-05-18

申请号：GB201420013

申请日：2014-11-11

Applicant: IBM

Inventor： TOBIAS WEBEL ,  MALCOLM S WARE ,  MICHAEL S FLOYD ,  CHARLES LEFURGY ,  KARTHICK RAJAMANI ,  ALAN DRAKE

IPC: G06F1/32

Abstract: Disclosed is a method of managing a multicore processor with a common supply rail connecting the processor cores. The method detects the core units indicating an idle state exits, and delays a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number. This is to reduce voltage droops due to several processor cores leaving the idle state at the same time and thus reduce the noise generated in the processor. The detecting may take place in a window of a set number of clock cycles, and the delaying may comprise throttling or postponing the command execution. The processor may have core power management logic with idle state exit register for turning on or off outputting an idle state value.