公开(公告)号：GB2494578B

公开(公告)日：2017-11-29

申请号：GB201222539

申请日：2011-05-25

Applicant: IBM

Inventor： JOHN BRUCE CARTER ,  LIXIN ZHANG ,  KARTHICK RAJAMANI ,  WILLIAM SPEIGHT ,  ELMOOTAZBELLAH NABIL ELNOZAHY ,  AHMED GHEITH ,  ERIC VAN HENSBERGEN

IPC: G06F9/54

公开(公告)号：GB2511986B

公开(公告)日：2020-03-04

申请号：GB201411244

申请日：2012-11-21

Applicant: IBM

Inventor： JEFFREY A STUECHELI ,  ERIC EUGENE RETTER ,  KARTHICK RAJAMANI ,  BRUCE MEALEY ,  JOHN BRUCE CARTER

IPC: G06F7/483 ,  G06F5/01

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

公开(公告)号：GB2494825B

公开(公告)日：2018-08-22

申请号：GB201300084

申请日：2011-06-08

Applicant: IBM

Inventor： NARESH NAYAR ,  FREEMAN LEIGH RAWSON III ,  KARTHICK RAJAMANI

IPC: G06F1/32

公开(公告)号：GB2605543A

公开(公告)日：2022-10-05

申请号：GB202209150

申请日：2020-10-21

Applicant: IBM

Inventor： SARAVANAN SETHURAMAN ,  VENKATA TAVVA ,  HILARY HUNTER ,  KARTHICK RAJAMANI ,  CHITRA SUBRAMANIAN

IPC: G11C11/16

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

公开(公告)号：GB2532210A

公开(公告)日：2016-05-18

申请号：GB201420013

申请日：2014-11-11

Applicant: IBM

Inventor： TOBIAS WEBEL ,  MALCOLM S WARE ,  MICHAEL S FLOYD ,  CHARLES LEFURGY ,  KARTHICK RAJAMANI ,  ALAN DRAKE

IPC: G06F1/32

Abstract: Disclosed is a method of managing a multicore processor with a common supply rail connecting the processor cores. The method detects the core units indicating an idle state exits, and delays a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number. This is to reduce voltage droops due to several processor cores leaving the idle state at the same time and thus reduce the noise generated in the processor. The detecting may take place in a window of a set number of clock cycles, and the delaying may comprise throttling or postponing the command execution. The processor may have core power management logic with idle state exit register for turning on or off outputting an idle state value.