公开(公告)号：SG109455A1

公开(公告)日：2005-03-30

申请号：SG200103837

申请日：1997-11-21

Applicant: IBM

Inventor： MICHEL SALIB MICHAIL ,  WILBUR DAVID PRICER ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.