公开(公告)号：JP2011125006A

公开(公告)日：2011-06-23

申请号：JP2010268938

申请日：2010-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AYIDN SUREN ,  PASCAL A NSAME ,  CHI-CHUEN CHAO-SUREN ,  SEBASTIAN THEODORE VENTRONE ,  HALL EZRA DANIEL

IPC: H04M3/00 ,  G06F17/28

CPC classification number: G06F17/289 ,  H04L12/1827 ,  H04L65/1056 ,  H04L65/1069 ,  H04L65/605 ,  H04L65/607 ,  H04M3/42391 ,  H04M3/56 ,  H04M2203/2061

Abstract: PROBLEM TO BE SOLVED: To provide a computer-implemented method and system of enabling concurrent real-time multi-language communication between multiple participants using a selective broadcast protocol. SOLUTION: The method includes the step of receiving at a first server a real-time communication from a first participant, the real-time communication being addressed to a second participant constructed in a first spoken language. A preferred spoken language of receipt of real-time communication is identified by the second participant. A determination is made whether the preferred spoken language of receipt is different than that of the first spoken language of the real-time communication. The real-time communication from the first spoken language is translated and delivered to the preferred spoken language of receipt of the second participant to create a translated real-time communication whenever the preferred spoken language is different than the first spoken language, and forwarded without translation when the preferred spoken language of the second participant is the same as the preferred spoken language of the first participant. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用选择性广播协议在多个参与者之间实现并发实时多语言通信的计算机实现的方法和系统。 解决方案：该方法包括以下步骤：在第一服务器处接收来自第一参与者的实时通信，所述实时通信被寻址到以第一语言构建的第二参与者。 由第二参与者确定接收实时通信的首选语言。 确定接收的首选语言是否与实时通信的第一语言的语言不同。 当首选语言不同于第一语言时，来自第一语言的实时通信被翻译并被传递到接收第二参与者的首选语言以创建翻译的实时通信，并且不转译地转发 当第二参与者的首选语言与第一参与者的首选语言相同时。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：SG106644A1

公开(公告)日：2004-10-29

申请号：SG200106659

申请日：2001-10-30

Applicant: IBM

Inventor： JOHN M COHN ,  ALVAR A DEAN ,  DAVID J HATHAWAY ,  DAVID E LACKEY ,  THOMAS E LEPSIC ,  SUSAN K LICHTENSTEIGER ,  SCOTT A TETREAULT ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F17/50 ,  H01L21/82

Abstract: Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into "bins", which are areas of the design. In this way, a semiconductor chip design may be "sliced" into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

公开(公告)号：SG90108A1

公开(公告)日：2002-07-23

申请号：SG200001383

申请日：2000-03-10

Applicant: IBM

Inventor： ALVAR A DEAN ,  KENNETH J GOODNOW ,  PATRICK E PERRY ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38 ,  G06F15/78 ,  G06F13/10 ,  G06F17/00 ,  G05F1/10

Abstract: A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.

公开(公告)号：SG109455A1

公开(公告)日：2005-03-30

申请号：SG200103837

申请日：1997-11-21

Applicant: IBM

Inventor： MICHEL SALIB MICHAIL ,  WILBUR DAVID PRICER ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

公开(公告)号：SG90028A1

公开(公告)日：2002-07-23

申请号：SG1998000547

申请日：1998-03-14

Applicant: IBM

Inventor： KENNETH J GOODNOW ,  CLARENCE R OGILVIE ,  WILBUR DAVID PRICER ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F9/46 ,  G06F12/08 ,  H04M3/00

Abstract: A call progress analysis system is provided which is generic to any telecommunications system with which it is used due to configurable detection parameters. A signal on a channel of the telecommunications system is detected in intervals of changing frequency composition and compared to stored pattern descriptors, each of which defines a different call progress signal. In an alternative embodiment of the invention, a frequency mask is computed that is specific to a user-defined call progress analysis class. This frequency mask is used to make the DSP receiver ignore frequencies that are not part of any call progress pattern in a particular class. The frequency mask can be used in a frequency detection mode or an energy detection mode. In either mode, the detector can be customized for each channel.