公开(公告)号：FR2340620A1

公开(公告)日：1977-09-02

申请号：FR7639828

申请日：1976-12-30

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  YU HWA N

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L21/88

公开(公告)号：CA1088382A

公开(公告)日：1980-10-28

申请号：CA271002

申请日：1977-02-03

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  YU HWA N

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H05K3/06

Abstract: A method of surface planarizing large scale integrated devices, including a double metal lift-off step is described. A first resist layer is deposited on an insulating layer which is formed over a first metal layer with a pattern structure. The resist layer is then masked by another metal layer. Then, a second resist layer is deposited over the metal masking, and is exposed and developed to delineate via holes therein. The metal masking, first resist layer and insulating layer are successively etched to define the via holes. During this procedure the second esist layer is automatically removed. A second metal layer is then deposited on the metal masking layer and in the defined via holes. The first resist layer is then lifted off which in turn accomplishes the double metal lift-off of the metal masking and the second metal layer. Subsequently, a third conductive metal pattern layer may, if desired, be deposited over the insulating layer and the metal filled via holes therein. A third resist layer is then deposited on the third metal layer and is exposed and developed to delineate a conductive pattern on the resist layer. The third resist layer is then exposed and developed and then the conductive pattern is formed on the planar surface of the device by lift-off reactive ion etching or other conventional techniques.

公开(公告)号：CA1139009A

公开(公告)日：1983-01-04

申请号：CA353720

申请日：1980-06-10

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  ROMANKIW LUBOMYR T

IPC: H05K1/05 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H05K1/11 ,  H05K3/32 ,  H05K3/46 ,  H05K1/18

Abstract: THIN FILM METAL PACKAGE FOR LSI CHIPS An integrated circuit board for mounting very high density chips of small size on its top surface including conductor planes for carrying very large values of .DELTA.I (transient current) is constructed with a plurality of essentially flat parallel power planes serving as conductive leads to the chip connectors (pins or solder balls). The land areas on the top surface of the board are connected to conductors below by integrated coaxial conductor extensions from the planes having a high degree of capacitive coupling to adjacent conductor planes. YO978-065

公开(公告)号：CA1095620A

公开(公告)日：1981-02-10

申请号：CA278853

申请日：1977-05-20

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  SPAMPINATO DOMINIC P

IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/40

Abstract: TWO-DEVICE MEMORY CELL A two-device memory cell for a memory array comprising a single storage capacitor having its terminals respectively coupled to one end of the respective source-drain paths of a pair of field-effect transistors so as to be in series therewith and float between a pair of bit/sense lines of the memory array respectively coupled to the other end of said paths and thereby provide a differential sense signal. Each of the gate electrodes of said pair of field effect transistors is coupled to the word line of said memory array. The differential sense signal obtained from such an arrangement obviates the need for a dummy cell to provide a reference level for detecting the state of the cell.

公开(公告)号：DE3071162D1

公开(公告)日：1985-11-14

申请号：DE3071162

申请日：1980-06-24

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  ROMANKIW LUBOMYR T

IPC: H05K1/05 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H05K1/11 ,  H05K3/32 ,  H05K3/46 ,  H01L23/54 ,  H05K1/00

Abstract: The board includes two parallel power plates (10, 11) separated by a dielectric layer (not shown). The plates (10, 11) are comprised of two mating metal sheets and are each provided with integral conductive pads (42, 40) and openings (41, 43). After assembly of the two plates (10, 11) and interleaved dielectric layer (not shown), each pad (40, 42) on the two plates is inserted into the coaxial opening (41, 43) in the opposite plate so as to form on the outside surfaces of the two plates (10, 11) areas comprising connection terminals for connecting LSI chips. Each of these area is insulated from the coplanar surrounding metal plate area by the dielectric layer (not shown).

公开(公告)号：FR2355358A1

公开(公告)日：1978-01-13

申请号：FR7714010

申请日：1977-05-03

Applicant: IBM

Inventor： MIERSCH EKKEHARD F ,  SPAMPINATO DOMINIC P

IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/40 ,  G11C7/00

Abstract: 1523094 Transistor memory cells INTERNATIONAL BUSINESS MACHINES CORP 25 April 1977 [17 June 1976] 17190/77 Heading H3T A memory cell comprises a single storage capacitor C, coupled in a series circuit including the source-drain paths of two FET's 1, 3 between two bit/sense lines B/S0, B/S1, the gate electrodes of the two transistors being coupled to the word line. The cell provides a differential signal and obviates the need for a dummy cell to provide a reference signal for detecting the cell state. To write data into the cell, the transistors 1,3 are turned on to allow capacitor C s to charge in one sense or the other, depending on whether a "0" or a " 1" is being written in. The transistors are then turned off to leave the capacitor floating. To read, the transistors are again turned on, and the differential voltage across the capacitor is sensed between the bit/sense lines.