公开(公告)号：US3573505A

公开(公告)日：1971-04-06

申请号：US3573505D

申请日：1968-07-15

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPAMPINATO DOMINIC P

IPC: G11C11/412 ,  H03K3/356 ,  H03K3/26

CPC classification number: H03K3/35606 ,  G11C11/412

Abstract: A memory cell in which the load devices thereof are unidirectional devices such as diodes, In the cell, where the storage devices are PNP or NPN devices, the diode load devices are disposed in the circuit such that the PN junctions of the diodes are backward biased. The storage devices, which are crosscoupled, and the diode load devices are connected at nodes to which gated drivers are also connected for the purpose of applying appropriate voltages to the nodes and, therefore, to the gate electrodes of the storage devices to change the conducting state of the storage devices during an active state. The gated drivers when turned on, also provide a portion of a current path to detect the conducting state of one or the other of the storage devices. In a quiescent state, the diode load devices in conjunction with a backward-biased PN junction portion of the OFF storage device form a nonlinear voltage divider which, because of their relative impedances, apply a voltage at the node of the OFF storage device to which the gate of the ON storage device is connected which maintains that storage device in the ON condition during the quiescent state. A bistable circuit and a nondestructive readout memory array are also disclosed.

公开(公告)号：US3541530A

公开(公告)日：1970-11-17

申请号：US3541530D

申请日：1968-01-15

Applicant: IBM

Inventor： SPAMPINATO DOMINIC P ,  TERMAN LEWIS M

IPC: G11C11/402 ,  G11C11/40 ,  H03K3/286

CPC classification number: G11C11/4023

公开(公告)号：US3535699A

公开(公告)日：1970-10-20

申请号：US3535699D

申请日：1968-01-15

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPAMPINATO DOMINIC P

IPC: G11C11/402 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C11/4023

公开(公告)号：CA1099347A

公开(公告)日：1981-04-14

申请号：CA271023

申请日：1977-02-03

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  SPAMPINATO DOMINIC P

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356 ,  H03K5/20 ,  G11C11/40 ,  H03F3/16

Abstract: CROSS-COUPLED CHARGE TRANSFER SENSE AMPLIFIER CIRCUITS Sense amplifiers employing charge-transfer techniques and cross-coupled devices for use with memory cell arrays or as comparators, polarity sensors and differential amplifiers are described which include a unique preamplifier circuit having cross-coupled actuable devices and which provides a cross-coupled charge-transfer feature. The sense amplifier also includes actuable devices which provide further amplification. The preamplifier circuit includes two precharge actuable devices which have their gate electrode. connected to the phase 1 line and which have their source electrode connected through separate capacitors to the phase 2 line. The terminals of the two preamplifier charge-transfer devices which are cross-coupled are also connected at the aforesaid circuit nodes and to the bit/sense lines and to the further amplification devices. The disclosure describes two embodiments of a preamplifier circuit, each of which is shown in combination with a plurality of different further amplification circuits.

公开(公告)号：CA1058321A

公开(公告)日：1979-07-10

申请号：CA230887

申请日：1975-07-07

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70

Abstract: DIFFERENTIAL CHARGE TRANSFER SENSE AMPLIFIER A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary Information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has Nigh sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

公开(公告)号：CA1097814A

公开(公告)日：1981-03-17

申请号：CA272841

申请日：1977-02-28

Applicant: IBM

Inventor： SPAMPINATO DOMINIC P

IPC: G11C11/41 ,  G11C8/08 ,  G11C8/10 ,  G11C11/407 ,  G11C11/413 ,  G11C11/40

Abstract: WORD LINE CLAMPING CIRCUIT of the Invention A word line clamping circuit for use with field effect transistor memories is disclosed which permits the clamping of the word line to a reference potential using a minimum of devices and without the consumption of d.c. power so that multi-level bit line potentials may be utilized during the memory cycle. This is achieved by connecting a field effect transistor (FET) between word line and ground under control of a word line decoder so that a node associated with the last mentioned FET is held in either an uncharged or charged condition depending on whether the decoder is selecting its associated word line or not selecting it. Because the unselected word lines are held at ground during a portion of the memory cycle when reading or writing of memory cells associated with a selected word line is taking place, any capacitive coupling which might change the content of cells associated with unselected word lines is avoided and, for whatever the reason, bit line potentials may now be changed to different levels without affecting information storage during the memory cycle. Two circuits are shown which, under control of the word line decoder, permit the grounding of unselected word lines during at least a major portion of the memory cycle.

公开(公告)号：FR2340598A1

公开(公告)日：1977-09-02

申请号：FR7639692

申请日：1976-12-23

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  SPAMPINATO DOMINIC P

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356 ,  G11C7/00 ,  G01R19/16

公开(公告)号：FR2316791A1

公开(公告)日：1977-01-28

申请号：FR7615575

申请日：1976-05-17

Applicant: IBM

Inventor： SPAMPINATO DOMINIC P

IPC: G01R19/165 ,  G11C11/404 ,  H03K3/356 ,  H03K3/286 ,  G01R19/16

Abstract: An f.e.t. flip flop sensor is designed to be threshold-independent. The threshold differences between the two branches are eliminated. A first and second transistor are connected in series to each of the two flip-flop transistors. The cross-coupling between the connecting point of the first and second transistor of the one branch runs with the gate electrode of the flip-flop transistor of the other branch. The flip-flop (10) has six active switching elements (12, 14, 16, 18, 20, 22) which consist of metal oxide semiconductor field-effect transistors. The flip-flop (10) is connected to a number of storage cells.

公开(公告)号：CA1092253A

公开(公告)日：1980-12-23

申请号：CA283444

申请日：1977-07-25

Applicant: IBM

Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/76

Abstract: FIELD EFFECT TRANSISTORS AND FABRICATION OF INTEGRATED CIRCUITS CONTAINING THE TRANSISTORS A field effect transistor (FET) wherein the field insulator is nonrecessed with respect to the source and drain regions, wherein the sides of the polysilicon gate electrode are self-aligned with respect to the nonconductive field insulator and neither overlap nor underlap the field insulator. The lateral dimensions and location of the gate correlate directly with the lateral dimensions and location of the channel region of the FET. The gate fabrication technique employed comprises delineating lithographic patterns twice in the same polysilicon layer; whereby the first lithographic pattern delineates regions to be used for sources and drains, and the next lithographic pattern forms the gate regions.

公开(公告)号：FR2344092A1

公开(公告)日：1977-10-07

申请号：FR7702070

申请日：1977-01-18

Applicant: IBM

Inventor： SPAMPINATO DOMINIC P

IPC: G11C11/41 ,  G11C8/08 ,  G11C8/10 ,  G11C11/407 ,  G11C11/413 ,  G11C7/00

Abstract: WORD LINE CLAMPING CIRCUIT of the Invention A word line clamping circuit for use with field effect transistor memories is disclosed which permits the clamping of the word line to a reference potential using a minimum of devices and without the consumption of d.c. power so that multi-level bit line potentials may be utilized during the memory cycle. This is achieved by connecting a field effect transistor (FET) between word line and ground under control of a word line decoder so that a node associated with the last mentioned FET is held in either an uncharged or charged condition depending on whether the decoder is selecting its associated word line or not selecting it. Because the unselected word lines are held at ground during a portion of the memory cycle when reading or writing of memory cells associated with a selected word line is taking place, any capacitive coupling which might change the content of cells associated with unselected word lines is avoided and, for whatever the reason, bit line potentials may now be changed to different levels without affecting information storage during the memory cycle. Two circuits are shown which, under control of the word line decoder, permit the grounding of unselected word lines during at least a major portion of the memory cycle.