公开(公告)号：DE3381505D1

公开(公告)日：1990-05-31

申请号：DE3381505

申请日：1983-12-21

Applicant: IBM

Inventor： MIRANKER GLEN SETH ,  WONG CHAK-KUEN

IPC: G06F7/24 ,  G06F7/22

Abstract: The invention is a bidirectional transposition exchange sorter for performing two overlapped sort operations overlapped in time with input/output operations so as to consume zero time. The sorter operates on the basis of a stack of cells, each of which contains two item storage locations (11, 12) and a comparator (13). The cells are arranged in a sorter stack configuration with a shift register monitor for each cell and an extra shift register position at the top of the sorter stack and also at the bottom. The monitor carries an indication of the current transfer mode for the cell.Each sort is carried out as two semi-sorts, input and output, which semi-sorts are time overlapped with the input and output operations typical of sort operations in computers. A portion of the sort operation takes place during an input step, so as to result in a partial reconfiguration of an unordered sequence at the end of the input semi-sort. Thereafter, a second portion of the sort operation takes place; the items exit in fully ordered sequence. After the sorter stack has been loaded with a first semi-sort of an unordered sequence, for example at the top end of the sorter stack, the second semi-sort may be overlapped with a first semi-sort of another unordered group of items being presented at the other end of the sorter stack, the bottom end in the example.

公开(公告)号：DE3367472D1

公开(公告)日：1986-12-11

申请号：DE3367472

申请日：1983-04-20

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  HSIEH HUNG-HUI ,  MIRANKER GLEN SETH

IPC: H03K19/173 ,  G06F7/50 ,  G06F7/505 ,  G06F7/506 ,  G06F7/508

Abstract: A logic carry circuit for carries involved in the addition of two binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 comprises AND gate 1, exclusive OR gate 9, transfer FET gate 14 connected to a carry-in line Cin, an inverter 19, an FET 18 connected to ground, and an OR gate 5, the carry output for digits A0 and B0 being C0, and the circuit being extended to the left and down for other digit pairs as shown. If A0 and B0 = "1", C0 = "1" due to AND gate 1 and OR gate 5, and line 20 immediately to the left of FET 14 is grounded by FET 18 due to exclusive OR 9. If only one of A0 and B0 = "1", and Cin = "1", Cin is transferred via FET 14 to OR gate 5, which produces C0 = "1". In the latter case if Cin had equalled "0", C0 would equal "0". The remainder of the circuit operates similarly.