公开(公告)号：DE3367472D1

公开(公告)日：1986-12-11

申请号：DE3367472

申请日：1983-04-20

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  HSIEH HUNG-HUI ,  MIRANKER GLEN SETH

IPC: H03K19/173 ,  G06F7/50 ,  G06F7/505 ,  G06F7/506 ,  G06F7/508

Abstract: A logic carry circuit for carries involved in the addition of two binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 comprises AND gate 1, exclusive OR gate 9, transfer FET gate 14 connected to a carry-in line Cin, an inverter 19, an FET 18 connected to ground, and an OR gate 5, the carry output for digits A0 and B0 being C0, and the circuit being extended to the left and down for other digit pairs as shown. If A0 and B0 = "1", C0 = "1" due to AND gate 1 and OR gate 5, and line 20 immediately to the left of FET 14 is grounded by FET 18 due to exclusive OR 9. If only one of A0 and B0 = "1", and Cin = "1", Cin is transferred via FET 14 to OR gate 5, which produces C0 = "1". In the latter case if Cin had equalled "0", C0 would equal "0". The remainder of the circuit operates similarly.

公开(公告)号：DE2621335A1

公开(公告)日：1976-12-23

申请号：DE2621335

申请日：1976-05-14

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  SCHUSTER STANLEY E

IPC: H03M1/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H03M1/00 ,  H03K13/05 ,  H03H7/00

公开(公告)号：DE68924479T2

公开(公告)日：1996-05-30

申请号：DE68924479

申请日：1989-12-13

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  MONTOYE ROBERT KEVIN

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F7/48

Abstract: Apparatus for shifting and determining if during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.

公开(公告)号：DE68924479D1

公开(公告)日：1995-11-09

申请号：DE68924479

申请日：1989-12-13

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  MONTOYE ROBERT KEVIN

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F7/48

Abstract: Apparatus for shifting and determining if during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.

公开(公告)号：DE2961384D1

公开(公告)日：1982-01-28

申请号：DE2961384

申请日：1979-02-01

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  SCHUSTER STANLEY EVERETT

IPC: H01L27/04 ,  G06F1/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/082 ,  H03K19/003 ,  H03K19/017 ,  H03K17/08 ,  H02H7/20 ,  H03K19/096 ,  G06F5/00

Abstract: A field effect transistor (FET) protection circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a combined gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range, by connecting a plurality of FET devices (3, 5) in series, by connecting the common nodes of successive series connected devices (3, 5) to a specified voltage source, by clamping the gate voltage, by providing timing pulses that define particular combinations of gate and drain to source device voltages, or by providing width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.

公开(公告)号：DE2711829A1

公开(公告)日：1977-10-13

申请号：DE2711829

申请日：1977-03-18

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  PARRISH JAMES THOMAS ,  SCHUSTER STANLEY EVERETT

IPC: H03M1/10 ,  H03K5/08 ,  H03M1/00 ,  H03M1/38 ,  H03K13/05

Abstract: A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.