公开(公告)号：DE2725614A1

公开(公告)日：1977-12-29

申请号：DE2725614

申请日：1977-06-07

Applicant: IBM

Inventor： MASOG CHARLES RAYMOND ,  PETRIE JEROME URBAN ,  MISHIMA YASUTSUGU

IPC: G06F9/32 ,  G06F9/38 ,  G06F13/06 ,  G06F9/00

Abstract: Instruction processing rate in a computer system is increased by providing a high speed data path to central processing unit (CPU) registers and including an auxiliary arithmetic and logic unit to enable updating the instruction address register (IAR) in one operation concurrently with a storage fetch whereby two storage fetches can be made within a single machine cycle. Normal instruction rate processing is retained by generating idle or dummy half cycles to enable a single storage fetch per machine cycle and thereby maintain flexibility for I/O instruction processing, for diagnostic purposes and for fetching the last byte or segment of an instruction having an odd number of bytes or segments.

公开(公告)号：FR2355331A1

公开(公告)日：1978-01-13

申请号：FR7714007

申请日：1977-05-03

Applicant: IBM

Inventor： MASOG CHARLES R ,  PETRIE JEROME U ,  MISHIMA YASUTSUGU

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/06

Abstract: Instruction processing rate in a computer system is increased by providing a high speed data path to central processing unit (CPU) registers and including an auxiliary arithmetic and logic unit to enable updating the instruction address register (IAR) in one operation concurrently with a storage fetch whereby two storage fetches can be made within a single machine cycle. Normal instruction rate processing is retained by generating idle or dummy half cycles to enable a single storage fetch per machine cycle and thereby maintain flexibility for I/O instruction processing, for diagnostic purposes and for fetching the last byte or segment of an instruction having an odd number of bytes or segments.