公开(公告)号：CA1012650A

公开(公告)日：1977-06-21

申请号：CA195289

申请日：1974-03-18

Applicant: IBM

Inventor： BERGLUND NEIL C ,  KERR JOHN W ,  PETRIE JEROME U

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/14

Abstract: Improved mode control is provided for a computer system whereby system mode can change for each asynchronously occurring interrupt. Mode control includes the functions of privileged instructions, masked interrupts, storage protection and address translation for expanded storage. Any combination of these functions can be active at any instant. Each interrupt level can select its own type of addressing control and with respect to any cycle of operation within the interrupt routine.

公开(公告)号：FR2355331A1

公开(公告)日：1978-01-13

申请号：FR7714007

申请日：1977-05-03

Applicant: IBM

Inventor： MASOG CHARLES R ,  PETRIE JEROME U ,  MISHIMA YASUTSUGU

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/06

Abstract: Instruction processing rate in a computer system is increased by providing a high speed data path to central processing unit (CPU) registers and including an auxiliary arithmetic and logic unit to enable updating the instruction address register (IAR) in one operation concurrently with a storage fetch whereby two storage fetches can be made within a single machine cycle. Normal instruction rate processing is retained by generating idle or dummy half cycles to enable a single storage fetch per machine cycle and thereby maintain flexibility for I/O instruction processing, for diagnostic purposes and for fetching the last byte or segment of an instruction having an odd number of bytes or segments.