公开(公告)号：JPH08264956A

公开(公告)日：1996-10-11

申请号：JP6445895

申请日：1995-03-23

Applicant: IBM

Inventor： MIZUMOTO SHOGO ,  TSUKADA YUTAKA

IPC: H01L23/498 ,  H05K3/46

Abstract: PURPOSE: To perform wiring freely in an SLC layer by maintaining the conductor path securing function of a through hole, which is electrically connected to a solder ball located at the opposite surface of the electrode of a semiconductor chip mounted on a multilayer substrate. CONSTITUTION: An SLC layer 13, which is provided on the first surface of a multilayer substrate, is connected to a conductor path 25 provided in a through hole 5 whose inside is filled and electrically connected to a solder bump 22 provided on the opposite surface of the first surface through the conductor path 25. Therefore, the distance of the wiring length between the connecting terminal of a substrate chip and the solder bump can be shortened, and thus the noises can be decreased. At the same time, since the mounting distance between the chips can be shortened, the fact contributes to high integration degree. Furthermore, since the wiring of the SLC layer 13 is not blocked by the presence of the through hole, the freedom of the wiring design can be secured.

公开(公告)号：JPH08242077A

公开(公告)日：1996-09-17

申请号：JP2970495

申请日：1995-02-17

Applicant: IBM

Inventor： MIZUMOTO SHOGO ,  TSUKADA YUTAKA

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/42 ,  H05K3/46

Abstract: PURPOSE: To electrically connect two or more layers to each other by a method, wherein there is formed a second insulation layer having a second via hole located directly above a first via hole, so as to come into contact with a first insulation layer. CONSTITUTION: A plating layer 330 made of a conductive layer is made in a first via hole 340, formed in a first insulation layer 310 on a board 300, and thereafter the first via hole 340 is filled with a metal, a metal paste, resin, etc. This filled surface is smoothed and another second insulation layer 320 is formed thereon, and in the second insulation layer 320, a second via hole 350 is formed substantially directly above the filled first via hole 340, and a plating layer 360 is formed on the second via hole 350. Thereby, two or more insulation layers 310, 320 can be connected electrically to each other.

公开(公告)号：JP2004335751A

公开(公告)日：2004-11-25

申请号：JP2003129874

申请日：2003-05-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WATANABE RYOICHI ,  YAMADA TATSUJI ,  MIZUMOTO SHOGO ,  KUMOKAWA FUMIO

IPC: C23F1/18 ,  C25D5/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K3/108 ,  C25D5/022 ,  H05K3/067 ,  H05K3/181 ,  H05K2203/1121

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed circuit board, which is able to etch seed layers, while preventing a circuit pattern from being etched.
SOLUTION: In a step of manufacturing the printed circuit board by a semi additive method, the seed layer 2 is formed by an electroless copper plating method, followed by forming the circuit pattern 4 by a copper electroplating method by using a resist pattern 3. After forming the circuit pattern 4, unnecessary portions of the seed layer 2 are etched. In performing etching, an etchant which has been refrigerated to have a temperature of 15°C or below is used. The lower the temperature of the etchant is, the larger the potential difference becomes between the seed layer 2 and the circuit pattern 4. The increase of the potential difference permits the seed layer 2 to be readily etched, and permits the circuit pattern 4 to be hardly etched owing to cathodic protection.
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