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    2.
    发明专利
    未知

    公开(公告)号：DE69205134D1

    公开(公告)日：1995-11-02

    申请号：DE69205134

    申请日：1992-12-02

    Applicant: IBM

    Inventor： TSUKADA YUTAKA

    IPC: H01L21/56 ,  H01L21/60

    Abstract: To replace a face-down bonded and resin encapsulated semiconductor chip with ease and without lowering reliability. A face-down bonded semiconductor chip 4 encapsulated with a resin 14 is removed from the substrate 2 with a cutting end mill 26. The resin 14 and bump electrodes 6 remaining on the substrate 2 are then cut with a finishing end mill to a height of about one half of the original height to planarize the surface. Another chip 4A having bump electrodes 6A is aligned with the bump electrodes 6 on the substrate 2, and bonded face down on the substrate. Finally, resin 14A is flowed into the gap between the chip 4A and the substrate 2 and around the chip 4A to encapsulate the chip.

    PRINTED WIRING BOARD AND PROCESS FOR PRODUCING THE SAME
    3.
    发明专利
    PRINTED WIRING BOARD AND PROCESS FOR PRODUCING THE SAME 未知

    公开(公告)号：AU2003277566A1

    公开(公告)日：2004-06-07

    申请号：AU2003277566

    申请日：2003-11-05

    Applicant: IBM

    Inventor： TSUKADA YUTAKA ,  MORI HIROYUKI

    IPC: H05K3/42 ,  H05K3/46

    Abstract: A defective electrical connection between conductor layers due to difference in thermal expansion between an insulating layer and the conductor layer is eliminated in the via hole in a printed wiring board Since the bonding face (18) between a first conductor (12) and a second conductor (15) has a large area on the bottom of a via, and the second conductor (15) has a fringe (flange) region (21) being boded to the surface (17) of a second insulating layer (14) at the outer circumferential part (20) of an opening in the second insulating layer on the bottom of the via, the printed wiring board is stabilized against a tensile stress resulting from a difference in thermal expansion between the insulating layer and the conductor layer and thereby a defective electrical connection between the conductor layers is eliminated in the via hole.

    5.
    发明专利
    未知

    公开(公告)号：DE10393589T5

    公开(公告)日：2005-12-22

    申请号：DE10393589

    申请日：2003-11-05

    Applicant: IBM

    Inventor： MORI HIROYUKI ,  TSUKADA YUTAKA

    IPC: H05K3/42 ,  H05K3/46

    Abstract: A defective electrical connection between conductor layers due to difference in thermal expansion between an insulating layer and the conductor layer is eliminated in the via hole in a printed wiring board Since the bonding face (18) between a first conductor (12) and a second conductor (15) has a large area on the bottom of a via, and the second conductor (15) has a fringe (flange) region (21) being boded to the surface (17) of a second insulating layer (14) at the outer circumferential part (20) of an opening in the second insulating layer on the bottom of the via, the printed wiring board is stabilized against a tensile stress resulting from a difference in thermal expansion between the insulating layer and the conductor layer and thereby a defective electrical connection between the conductor layers is eliminated in the via hole.

    6.
    发明专利
    未知

    公开(公告)号：DE69205134T2

    公开(公告)日：1996-05-02

    申请号：DE69205134

    申请日：1992-12-02

    Applicant: IBM

    Inventor： TSUKADA YUTAKA

    IPC: H01L21/56 ,  H01L21/60

    Abstract: To replace a face-down bonded and resin encapsulated semiconductor chip with ease and without lowering reliability. A face-down bonded semiconductor chip 4 encapsulated with a resin 14 is removed from the substrate 2 with a cutting end mill 26. The resin 14 and bump electrodes 6 remaining on the substrate 2 are then cut with a finishing end mill to a height of about one half of the original height to planarize the surface. Another chip 4A having bump electrodes 6A is aligned with the bump electrodes 6 on the substrate 2, and bonded face down on the substrate. Finally, resin 14A is flowed into the gap between the chip 4A and the substrate 2 and around the chip 4A to encapsulate the chip.

    Hole forming method, and hole forming device
    7.
    发明专利
    Hole forming method, and hole forming device 审中-公开
    孔形成方法和孔形成装置

    公开(公告)号：JP2004243404A

    公开(公告)日：2004-09-02

    申请号：JP2003038532

    申请日：2003-02-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： YASUDA MASAHARU ,  MAEDA YOJI ,  YAMANAKA KIMIHIRO ,  TSUKADA YUTAKA

    IPC: B23K26/00 ,  B23K26/04 ,  B23K26/38 ,  B23K101/42 ,  H05K3/00

    CPC classification number: B23K26/042 ,  B23K26/382 ,  B23K26/384 ,  B23K2201/42 ,  B23K2203/50 ,  H05K3/0026

    Abstract: PROBLEM TO BE SOLVED: To provide a hole forming method and a hole forming device for forming a hole in which the hole diameters of the upper part and the bottom part are the same in hole forming using a laser. SOLUTION: The hole forming device is composed in such a manner that a laser 10 is vertically irradiated to a substrate 12, and a hole with a taper shape in which the hole diameter in the bottom part is smaller than that in the upper part. Further, in the hole forming device, the tapered hole is irradiated with the laser 10 so as to be tilted to the substrate 12, and the hole diameters in the upper part and the bottom part are made uniform. By applying the laser 10 so as to be tilted in this way, a straight hole 14 can be formed. COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于形成孔的孔形成方法和孔形成装置，其中上部和下部的孔直径在使用激光的孔形成中相同。 解决方案：孔形成装置以激光器10垂直照射到基板12的方式构成，并且具有锥形形状的孔，其中底部的孔直径小于上部的孔直径 部分。 此外，在孔形成装置中，锥形孔用激光器10照射以与基板12倾斜，并使上部和底部的孔直径均匀。 通过以这种方式施加激光10以使其倾斜，可以形成直孔14。 版权所有（C）2004，JPO＆NCIPI

    PRINTED-WIRING BOARD, ITS MANUFACTURING METHOD, AND PHOTOMASK USED THEREFOR
    8.
    发明专利
    PRINTED-WIRING BOARD, ITS MANUFACTURING METHOD, AND PHOTOMASK USED THEREFOR 失效

    公开(公告)号：JP2002111225A

    公开(公告)日：2002-04-12

    申请号：JP2000282149

    申请日：2000-09-18

    Applicant: IBM

    Inventor： YAMADA SHINJI ,  TSUKADA YUTAKA

    IPC: H05K3/46 ,  B32B3/02 ,  B32B27/34 ,  B32B27/38 ,  H05K3/00

    Abstract: PROBLEM TO BE SOLVED: To provide a printed-wiring board for improving the yield of a printed- wiring board, especially a build-up multilayer printed-wiring board, the manufacturing method of the printed-wiring board, and a photomask used for the method. SOLUTION: The printed-wiring board includes a base substrate 2 containing conductor circuit patterns 6a and 6b on the surface and at least a layer of resin layer 3 provided on the base layer. In the printed-wiring board, the resin layer is formed by a photosensitive resin, and a photosensitive resin layer on the conductive circuit pattern is exposed by the amount of exposure according to the area of the conductive circuit patterns for formation.

    Design of spacer resin pattern useful for reduction of connection loss of light between light emitting element or light receiving element and optical waveguide on semiconductor
    9.
    发明专利
    Design of spacer resin pattern useful for reduction of connection loss of light between light emitting element or light receiving element and optical waveguide on semiconductor 有权
    用于减少发光元件或光接收元件之间的光连接损失的半球形树脂图案的设计

    公开(公告)号：JP2013222075A

    公开(公告)日：2013-10-28

    申请号：JP2012093713

    申请日：2012-04-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： TOKUNARI MASAO ,  NAKANO DAIKI ,  TSUKADA YUTAKA ,  TORIYAMA KAZUSHIGE

    IPC: G02B6/122

    CPC classification number: G02B6/4236 ,  G02B6/4214 ,  H01L25/167 ,  H01L31/0232 ,  H01L33/58 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To form a spacer resin (SR) pattern layer for accurate alignment of a light emitting element or a light receiving element with both of an optical waveguide (WG) pattern layer and an electric circuit (EC) pattern layer, from a wafer level of a semiconductor.SOLUTION: A base layer which has a through hole (via) provided to electrically communicate with an electric circuit (EC) pattern layer and is made of a resin is formed on a semiconductor (GaAs) wafer. A truncated cone or polygonal pyramid-shaped three-dimensional reflecting surface is formed to guide output of emitted light to or input of received light from an optical waveguide (WG) pattern layer. A metal film being doughnut-shaped, circular, or polygonal in plan view is vapor-deposited in a prescribed range from a center positioned on the basis of the position of the through hole. A cone or pyramid-shaped mold is stamped to the center. The direction of light is corrected by a formed taper structure to increase tolerance for accuracy and to reduce light loss.

    Abstract translation: 要解决的问题：为了形成用于将光发射元件或光接收元件与光波导（WG）图案层和电路（EC）图案层两者精确对准的间隔树脂（SR）图案层，从 晶片级半导体。解决方案：在半导体（GaAs）晶片上形成具有设置用于与电路（EC）图案层电连通并由树脂制成的通孔（通孔））的基底层。 形成截锥体或多角锥形的三维反射表面以将发射的光的输出引导到光波导（WG）图案层的接收光或从光波导（WG）图案层输入。 在平面图中为圆环状，圆形或多边形的金属膜从规定范围内从基于通孔的位置的中心蒸镀。 锥体或金字塔形模具被冲压到中心。 通过形成的锥形结构校正光的方向，以增加准确性的公差并减少光损失。

    SOLDERING METHOD AND SOLDERING DEVICE
    10.
    发明专利
    SOLDERING METHOD AND SOLDERING DEVICE 失效

    公开(公告)号：JPH0992682A

    公开(公告)日：1997-04-04

    申请号：JP24424695

    申请日：1995-09-22

    Applicant: IBM

    Inventor： KODAMA YASUSHI ,  TSUCHIDA SHUHEI ,  TSUKADA YUTAKA ,  ORII YASUMITSU ,  OKUMA HIDEO

    IPC: H01L21/60 ,  B23K1/005 ,  B23K1/012 ,  H01L21/603 ,  H05K3/34

    Abstract: PROBLEM TO BE SOLVED: To grip a chip by a head to solder keeping the molten solder by with molten. SOLUTION: Solder bumps 3 formed on a chip 1 face the electrodes 11 on a mounting board 10. Then the solder bumps 3 are heated to their melting points by heating a heating block 21 provided on the rear surface side of the chip 1. It is preferable to provide another heating block 22 on the rear surface of the board 10. With the solder bumps 3 molten, the bumps 3 are soldered to the electrodes 11 by bringing the bumps 3 into contact with the electrodes 11.

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