公开(公告)号：GB2581051B

公开(公告)日：2020-12-02

申请号：GB202005136

申请日：2018-09-21

Applicant: IBM

Inventor： MONA EBRISH ,  OLEG GLUSCHENKOV

IPC: H01L29/78

公开(公告)号：GB2581051A

公开(公告)日：2020-08-05

申请号：GB202005136

申请日：2018-09-21

Applicant: IBM

Inventor： MONA EBRISH ,  OLEG GLUSCHENKOV

IPC: H01L29/78

Abstract: A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.