中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.017 seconds)

    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation
    1.
    发明专利
    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation 未知

    公开(公告)号：GB2631071B

    公开(公告)日：2025-04-16

    申请号：GB202414743

    申请日：2023-03-23

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

    IPC: H10D62/13 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

    Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

    Large grain copper interconnect lines for MRAM
    4.
    发明专利
    Large grain copper interconnect lines for MRAM 未知

    公开(公告)号：GB2607792A

    公开(公告)日：2022-12-14

    申请号：GB202212342

    申请日：2021-01-05

    Applicant: IBM

    Inventor： YASIR SULEHRIA ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV ,  DEVIKA SIL

    IPC: H01L43/08

    Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

    Mram devices containing a hardened gap fill dielectric material
    5.
    发明专利
    Mram devices containing a hardened gap fill dielectric material 未知

    公开(公告)号：GB2603684A

    公开(公告)日：2022-08-10

    申请号：GB202204972

    申请日：2020-09-22

    Applicant: IBM

    Inventor： ALEXANDER REZNICEK ,  DEVIKA SIL ,  OLEG GLUSCHENKOV ,  YASIR SULEHRIA

    IPC: H01L43/02 ,  H01L43/08

    Abstract: A hardened gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.

    Reducing series resistance between source and/or drain regions and a channel region
    6.
    发明专利
    Reducing series resistance between source and/or drain regions and a channel region 未知

    公开(公告)号：GB2581051A

    公开(公告)日：2020-08-05

    申请号：GB202005136

    申请日：2018-09-21

    Applicant: IBM

    Inventor： MONA EBRISH ,  OLEG GLUSCHENKOV

    IPC: H01L29/78

    Abstract: A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.

    Extreme ultra violet (EUV) radiation source
    7.
    发明专利
    Extreme ultra violet (EUV) radiation source 未知

    公开(公告)号：GB2544940A

    公开(公告)日：2017-05-31

    申请号：GB201704618

    申请日：2015-09-01

    Applicant: IBM

    Inventor： VEERESH VIDYADHAR DESHPANDE ,  SADANAND VINAYAK DESHPANDE ,  DANIEL CORLISS ,  OLEG GLUSCHENKOV ,  SIVARAMA KRISHNAN

    IPC: H05G2/00

    Abstract: An extreme ultraviolet (EUV) radiation source pellet(8) includes at least one metal particle (30) embedded within a heavy noble gas cluster (20) contained within a noble gas shell cluster (10). The EUV radiation source assembly can be activated by a sequential irradiation of at least one first laser pulse and at least one second laser pulse. Each first laser pulse generates plasma by detaching outer orbital electrons from the at least one metal particle (30) and releasing the electrons into the heavy noble gas cluster(20). Each second laser pulse amplifies the plasma embedded in the heavy noble gas cluster (20) triggering a laser-driven self-amplifying process. The amplified plasma induces inter-orbital electron transitions in heavy noble gas and other constitute atoms leading to emission of EUV radiation. The laser pulsing units can be combined with a source pellet generation unit to form an integrated EUV source system.

    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation
    9.
    发明专利
    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation 未知

    公开(公告)号：GB2631071A

    公开(公告)日：2024-12-18

    申请号：GB202414743

    申请日：2023-03-23

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

    IPC: H01L29/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

    Large grain copper interconnect lines for MRAM
    10.
    发明专利
    Large grain copper interconnect lines for MRAM 未知

    公开(公告)号：GB2607792B

    公开(公告)日：2024-12-18

    申请号：GB202212342

    申请日：2021-01-05

    Applicant: IBM

    Inventor： ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV ,  YASIR SULEHRIA ,  DEVIKA SIL

    IPC: H10N50/01

    Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

Patent Agency Ranking