公开(公告)号：DE69026503D1

公开(公告)日：1996-05-15

申请号：DE69026503

申请日：1990-07-31

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/82 ,  H01L21/768 ,  H01L27/10

公开(公告)号：DE69211329D1

公开(公告)日：1996-07-11

申请号：DE69211329

申请日：1992-03-27

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK

IPC: H01L21/8249 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  H01L21/82

Abstract: A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure including the steps of: a) elaborating a P type silicon substrate (23) having a major surface provided with a plurality of isolation regions (28) as the initial structure; b) delineating polysilicon lands (32A) above certain isolation regions (28E); c) forming N-well regions (35) into the substrate (23) where bulk PFETs are to be subsequently formed; d) forming insulator encapsulated conductive polysilicon studs (39A, ...) to be used in particular as gate electrodes at desired locations of the structure; e) forming self-aligned source/drain regions (50) of the bulk NFETs into the substrate; f) forming self-aligned source/drain regions (52) of the bulk PFETs and pPFETs into the substrate and polysilicon lands respectively; and, g) forming contact regions (53) to the desired locations including said source/drain regions. In particular, the method has applicability in the forming of polysilicon PFETs that are extensively used as load devices in six device (6D) SRAM cells.

公开(公告)号：DE69023765T2

公开(公告)日：1996-06-20

申请号：DE69023765

申请日：1990-07-31

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK ,  VALLET VINCENT

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/00 ,  H01L27/092 ,  H01L27/11 ,  H01L21/82 ,  H01L21/768

Abstract: A stacked semiconductor structure including: a base structure comprised of a semiconductor substrate (18/19) having active regions (21) of devices (N1, ...) formed therein and a plurality of polysilicon lines (23-1, ...) formed thereupon; a first thick passivating layer (26/27) formed onto said substrate having a set of first metal contact studs (30-1, ...) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, ...), the upper part of said first contact studs defining either gate electrodes of sPFET devices (P2) and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; a thin insulating layer (31) forming the gate dielectric layer of said PFET devices and provided with contact openings (32-1, ...) to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands (33-1, ...) formed over said thin insulating layer (31), a certain portion thereof define the source, drain and channel region of the body of a determined PFET device (P2); at least one of said source and drain regions contacting a first metal contact stud (30-4) through a contact opening; a second thick passivating layer (35/36) having a set of second metal contact studs (38-1, ...) therein contacting at least one of said polysilicon lands (33-1, ...) and/or said first contact studs (30-1, ...); the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. a first metal interconnection configuration having metal lands (39-1, ...) electrically contacting at least one of said second metal contact studs (38-1, ...); and a final insulating film (40). The structure of the present invention can be advantageously used in chips implementing 6D SRAM cells with stacked PFETs as load devices in CMOS FET technology.

公开(公告)号：DE69526585D1

公开(公告)日：2002-06-06

申请号：DE69526585

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F3/24 ,  G05F3/26 ,  G05F3/30 ,  H03F1/30

Abstract: The present invention relates to a reference current generator that is compensated in temperature when resistors with high temperature coefficients (such as those that can be found in pure digital CMOS technology) are used. Basically, the novel reference current generator (15) that is biased between first and second supply voltages (Vdd, Gnd) is constructed around two current sources (11, 12) that generate respective first (I1) and second (I2) currents whose temperature coefficient (TC1, TC2) is negative because they incorporate such resistors. The second current is mirrored, then subtracted to the first current at a node (17) to generate a primary current (I = I1 - I2). By a proper design of the current source parameters, the temperature coefficient of the primary current (i.e. TC = dI/dT) can be cancelled. This primary current is applied to the drain of a diode-connected FET device (T11) whose source is connected to said second supply voltage (Gnd). The reference voltage (Vref) that is available on the common drain/gate thereof is applied to the gate of an output NFET device (T12) whose source is also tied to said second supply voltage. The reference current (Iref) which is directly derived from the said primary current (by a proportionality factor) is outputted at the drain (14) of said output NFET device. As a result, a fully temperature compensated reference current (dIref/dT = 0) may be obtained.

公开(公告)号：DE69513185T2

公开(公告)日：2000-06-21

申请号：DE69513185

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F1/618 ,  G05F3/26 ,  H03F3/345 ,  H03L7/089

Abstract: A highly symmetrical bi-directional current source (18) biased between first and second (Vdd, Gnd) supply voltages in CMOS FET technology comprises an current generator (11') which includes an innovative circuit (19) and a standard switching circuit (12). The switching circuit consists of two pairs of complementary FET devices that are paralleled with a unity gain operational amplifier connected between their common nodes. In a first branch, a diode-connected PFET device (T1) and a current supply (13) are connected in series as standard to generate a reference current (Iref) as standard. The second branch includes the standard first mirroring device (T3), first and second resistively-connected complementary devices (T10,T11) with an intermediate node (20) coupled therebetween and a second mirroring NFET device (T12) are all connected in series. The third branch is formed by first (T2) and second (T5) output FET devices with said switching circuit connected between their drains to select either the source or the sink current to be outputted at the output node (14) as the output current (Iout). By designing the type and the size of corresponding devices in the second and third branches to be substantially the same, an excellent impedance matching can be obtained therebetween. Said innovative circuit further includes an operational amplifier based circuit (OP2, R) whose positive input is connected to said intermediate node, its negative input is connected to one (15) of said common node and the output is connected to the node (21) formed by the gates of said second mirroring and output devices so that there is no potential difference between its inputs.

公开(公告)号：DE69513185D1

公开(公告)日：1999-12-09

申请号：DE69513185

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F1/618 ,  G05F3/26 ,  H03F3/345 ,  H03L7/089

Abstract: A highly symmetrical bi-directional current source (18) biased between first and second (Vdd, Gnd) supply voltages in CMOS FET technology comprises an current generator (11') which includes an innovative circuit (19) and a standard switching circuit (12). The switching circuit consists of two pairs of complementary FET devices that are paralleled with a unity gain operational amplifier connected between their common nodes. In a first branch, a diode-connected PFET device (T1) and a current supply (13) are connected in series as standard to generate a reference current (Iref) as standard. The second branch includes the standard first mirroring device (T3), first and second resistively-connected complementary devices (T10,T11) with an intermediate node (20) coupled therebetween and a second mirroring NFET device (T12) are all connected in series. The third branch is formed by first (T2) and second (T5) output FET devices with said switching circuit connected between their drains to select either the source or the sink current to be outputted at the output node (14) as the output current (Iout). By designing the type and the size of corresponding devices in the second and third branches to be substantially the same, an excellent impedance matching can be obtained therebetween. Said innovative circuit further includes an operational amplifier based circuit (OP2, R) whose positive input is connected to said intermediate node, its negative input is connected to one (15) of said common node and the output is connected to the node (21) formed by the gates of said second mirroring and output devices so that there is no potential difference between its inputs.

公开(公告)号：DE69211329T2

公开(公告)日：1996-11-28

申请号：DE69211329

申请日：1992-03-27

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK

IPC: H01L21/8249 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  H01L21/82

Abstract: A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure including the steps of: a) elaborating a P type silicon substrate (23) having a major surface provided with a plurality of isolation regions (28) as the initial structure; b) delineating polysilicon lands (32A) above certain isolation regions (28E); c) forming N-well regions (35) into the substrate (23) where bulk PFETs are to be subsequently formed; d) forming insulator encapsulated conductive polysilicon studs (39A, ...) to be used in particular as gate electrodes at desired locations of the structure; e) forming self-aligned source/drain regions (50) of the bulk NFETs into the substrate; f) forming self-aligned source/drain regions (52) of the bulk PFETs and pPFETs into the substrate and polysilicon lands respectively; and, g) forming contact regions (53) to the desired locations including said source/drain regions. In particular, the method has applicability in the forming of polysilicon PFETs that are extensively used as load devices in six device (6D) SRAM cells.

公开(公告)号：DE69026503T2

公开(公告)日：1996-11-14

申请号：DE69026503

申请日：1990-07-31

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/82 ,  H01L21/768 ,  H01L27/10

公开(公告)号：DE69023765D1

公开(公告)日：1996-01-04

申请号：DE69023765

申请日：1990-07-31

Applicant: IBM

Inventor： CEDERBAUM CARL ,  CHANCLOU ROLAND ,  COMBES MYRIAM ,  MONE PATRICK ,  VALLET VINCENT

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/00 ,  H01L27/092 ,  H01L27/11 ,  H01L21/82 ,  H01L21/768

Abstract: A stacked semiconductor structure including: a base structure comprised of a semiconductor substrate (18/19) having active regions (21) of devices (N1, ...) formed therein and a plurality of polysilicon lines (23-1, ...) formed thereupon; a first thick passivating layer (26/27) formed onto said substrate having a set of first metal contact studs (30-1, ...) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, ...), the upper part of said first contact studs defining either gate electrodes of sPFET devices (P2) and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; a thin insulating layer (31) forming the gate dielectric layer of said PFET devices and provided with contact openings (32-1, ...) to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands (33-1, ...) formed over said thin insulating layer (31), a certain portion thereof define the source, drain and channel region of the body of a determined PFET device (P2); at least one of said source and drain regions contacting a first metal contact stud (30-4) through a contact opening; a second thick passivating layer (35/36) having a set of second metal contact studs (38-1, ...) therein contacting at least one of said polysilicon lands (33-1, ...) and/or said first contact studs (30-1, ...); the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. a first metal interconnection configuration having metal lands (39-1, ...) electrically contacting at least one of said second metal contact studs (38-1, ...); and a final insulating film (40). The structure of the present invention can be advantageously used in chips implementing 6D SRAM cells with stacked PFETs as load devices in CMOS FET technology.