公开(公告)号：DE60303046T2

公开(公告)日：2006-07-27

申请号：DE60303046

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：DE60303046D1

公开(公告)日：2006-02-02

申请号：DE60303046

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：AU2003250884A1

公开(公告)日：2004-02-23

申请号：AU2003250884

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：DE69526585D1

公开(公告)日：2002-06-06

申请号：DE69526585

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F3/24 ,  G05F3/26 ,  G05F3/30 ,  H03F1/30

Abstract: The present invention relates to a reference current generator that is compensated in temperature when resistors with high temperature coefficients (such as those that can be found in pure digital CMOS technology) are used. Basically, the novel reference current generator (15) that is biased between first and second supply voltages (Vdd, Gnd) is constructed around two current sources (11, 12) that generate respective first (I1) and second (I2) currents whose temperature coefficient (TC1, TC2) is negative because they incorporate such resistors. The second current is mirrored, then subtracted to the first current at a node (17) to generate a primary current (I = I1 - I2). By a proper design of the current source parameters, the temperature coefficient of the primary current (i.e. TC = dI/dT) can be cancelled. This primary current is applied to the drain of a diode-connected FET device (T11) whose source is connected to said second supply voltage (Gnd). The reference voltage (Vref) that is available on the common drain/gate thereof is applied to the gate of an output NFET device (T12) whose source is also tied to said second supply voltage. The reference current (Iref) which is directly derived from the said primary current (by a proportionality factor) is outputted at the drain (14) of said output NFET device. As a result, a fully temperature compensated reference current (dIref/dT = 0) may be obtained.

公开(公告)号：DE69513185T2

公开(公告)日：2000-06-21

申请号：DE69513185

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F1/618 ,  G05F3/26 ,  H03F3/345 ,  H03L7/089

Abstract: A highly symmetrical bi-directional current source (18) biased between first and second (Vdd, Gnd) supply voltages in CMOS FET technology comprises an current generator (11') which includes an innovative circuit (19) and a standard switching circuit (12). The switching circuit consists of two pairs of complementary FET devices that are paralleled with a unity gain operational amplifier connected between their common nodes. In a first branch, a diode-connected PFET device (T1) and a current supply (13) are connected in series as standard to generate a reference current (Iref) as standard. The second branch includes the standard first mirroring device (T3), first and second resistively-connected complementary devices (T10,T11) with an intermediate node (20) coupled therebetween and a second mirroring NFET device (T12) are all connected in series. The third branch is formed by first (T2) and second (T5) output FET devices with said switching circuit connected between their drains to select either the source or the sink current to be outputted at the output node (14) as the output current (Iout). By designing the type and the size of corresponding devices in the second and third branches to be substantially the same, an excellent impedance matching can be obtained therebetween. Said innovative circuit further includes an operational amplifier based circuit (OP2, R) whose positive input is connected to said intermediate node, its negative input is connected to one (15) of said common node and the output is connected to the node (21) formed by the gates of said second mirroring and output devices so that there is no potential difference between its inputs.

公开(公告)号：DE69513185D1

公开(公告)日：1999-12-09

申请号：DE69513185

申请日：1995-12-06

Applicant: IBM

Inventor： GIRARD PHILIPPE ,  MONE PATRICK

IPC: G05F1/618 ,  G05F3/26 ,  H03F3/345 ,  H03L7/089

Abstract: A highly symmetrical bi-directional current source (18) biased between first and second (Vdd, Gnd) supply voltages in CMOS FET technology comprises an current generator (11') which includes an innovative circuit (19) and a standard switching circuit (12). The switching circuit consists of two pairs of complementary FET devices that are paralleled with a unity gain operational amplifier connected between their common nodes. In a first branch, a diode-connected PFET device (T1) and a current supply (13) are connected in series as standard to generate a reference current (Iref) as standard. The second branch includes the standard first mirroring device (T3), first and second resistively-connected complementary devices (T10,T11) with an intermediate node (20) coupled therebetween and a second mirroring NFET device (T12) are all connected in series. The third branch is formed by first (T2) and second (T5) output FET devices with said switching circuit connected between their drains to select either the source or the sink current to be outputted at the output node (14) as the output current (Iout). By designing the type and the size of corresponding devices in the second and third branches to be substantially the same, an excellent impedance matching can be obtained therebetween. Said innovative circuit further includes an operational amplifier based circuit (OP2, R) whose positive input is connected to said intermediate node, its negative input is connected to one (15) of said common node and the output is connected to the node (21) formed by the gates of said second mirroring and output devices so that there is no potential difference between its inputs.