公开(公告)号：JP2007234011A

公开(公告)日：2007-09-13

申请号：JP2007038736

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CAPEK PETER G ,  DERBY JEFFREY HASKELL ,  MONTOYE ROBERT K

IPC: G06F9/34

CPC classification number: G06F9/3012 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/384

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for managing a register map for indirect register file access based on a map in a processor. SOLUTION: The management mechanism includes a register mapping including a map set, and each map of the map set has a plurality of map registers. An actual register set is accessed indirectly by the processor via map entries of the map set. The number of actual registers in the actual register set is larger than the number of map entries in the map set, and the map entries of the map set refer only to subsets of the actual register set at an optional time point. The mechanism includes the step of updating a plurality of map entries of at least one map of the map set in response to the execution of a single update instruction to manage update to a plurality of entries of the map set of the register mapping. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于基于处理器中的映射管理用于间接寄存器文件访问的寄存器映射的机制。 解决方案：管理机制包括包括地图集的寄存器映射，并且映射集合的每个映射具有多个映射寄存器。 处理器通过映射集的映射条目间接访问实际的寄存器集。 实际寄存器组中的实际寄存器的数量大于地图集中的地图条目的数量，映射集的映射条目仅指可选时间点的实际寄存器集的子集。 该机制包括响应于单个更新指令的执行来更新地图集合的至少一个地图的多个地图条目的步骤，以管理对寄存器映射的地图集合的多个条目的更新。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2319366B

公开(公告)日：2001-04-11

申请号：GB9720302

申请日：1997-09-25

Applicant: IBM

Inventor： AUERBACH DANIEL J ,  CRAFT DAVID J ,  MONTOYE ROBERT K

IPC: H03M7/30 ,  G06F9/45 ,  G06F9/22

公开(公告)号：GB2319366A

公开(公告)日：1998-05-20

申请号：GB9720302

申请日：1997-09-25

Applicant: IBM

Inventor： AUERBACH DANIEL J ,  CRAFT DAVID J ,  MONTOYE ROBERT K

IPC: H03M7/30 ,  G06F9/45 ,  G06F9/22

Abstract: In a data processing system (10, Figure 1), a set of compiled microcode is parsed 21, into multiple microcode segments, wherein each of these microcode segments is of equal length. Each of the microcode segments is then individually compressed 22 using a data-compression routine. Next, all of these compressed microcode segments are concatenated and linked 23 to yield a set of compressed executable microcode. Finally, the starting address for each of the compressed microcode segments is stored 24 in an indexer. By so doing, the required memory for storing the compressed executable microcode is reduced.

公开(公告)号：DE102013214418A1

公开(公告)日：2014-02-13

申请号：DE102013214418

申请日：2013-07-24

Applicant: IBM

Inventor： LAM CHUNG H ,  LI JING ,  MONTOYE ROBERT K

IPC: G11C7/06

Abstract: Eine beispielhafte Ausführungsform ist eine Schaltung zum Ermitteln eines Binärwertes einer Speicherzelle. Die Schaltung weist Parallelkondensatoren mit unterschiedlichen Kapazitäten auf, um selektiv eine Verbindung mit der Speicherzelle herzustellen, und eine Steuereinheit, die so konfiguriert ist, dass die Parallelkondensatoren iterativ auf eine erste Spannung aufgeladen werden, bis ein ausgewählter Parallelkondensator bewirkt, dass die erste Spannung innerhalb eines vordefinierten Zeitbereiches über die Speicherzelle auf eine erste Vergleichsspannung abnimmt, auf der Grundlage des ausgewählten Parallelkondensators ein Binärwert der höchstwertigen Bits der Speicherzelle ermittelt wird, nach dem Ermitteln des Binärwertes der höchstwertigen Bits der Speicherzelle der ausgewählte Parallelkondensator auf eine zweite Spannung aufgeladen wird, und auf der Grundlage einer Abnahme der zweiten Spannung am ausgewählten Parallelkondensator über die Speicherzelle ein Binärwert der niedrigstwertigen Bits der Speicherzelle ermittelt wird.

公开(公告)号：CA1229384A

公开(公告)日：1987-11-17

申请号：CA508658

申请日：1986-05-07

Applicant: IBM

Inventor： KIRKPATRICK EDWARD S ,  KRONSTADT ERIC P ,  MONTOYE ROBERT K ,  WILCKE WINFRIED W

IPC: H03K17/00 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G06F11/267 ,  G06F11/26

Abstract: TEST CIRCUIT FOR DIFFERENTIAL CASCODE VOLTAGE SWITCH An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and ? switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.