公开(公告)号：CA1229384A

公开(公告)日：1987-11-17

申请号：CA508658

申请日：1986-05-07

Applicant: IBM

Inventor： KIRKPATRICK EDWARD S ,  KRONSTADT ERIC P ,  MONTOYE ROBERT K ,  WILCKE WINFRIED W

IPC: H03K17/00 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G06F11/267 ,  G06F11/26

Abstract: TEST CIRCUIT FOR DIFFERENTIAL CASCODE VOLTAGE SWITCH An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and ? switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.

公开(公告)号：CA1233272A

公开(公告)日：1988-02-23

申请号：CA482187

申请日：1985-05-23

Applicant: IBM

Inventor： KRONSTADT ERIC P ,  GANDHI SHARAD P

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G11C11/401 ,  G11C7/00 ,  G11C11/34

Abstract: DISTRIBUTED CACHE IN DYNAMIC RAMS A microcomputer memory system is organized into a plurlaity of banks (16). Each bank consists of an array of static column mode dynamic random access memories (DRAMs) of 5 the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (15) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the 5 contents of the distributed cache with the contents of the addressed row for that bank.

公开(公告)号：CA1228170A

公开(公告)日：1987-10-13

申请号：CA482001

申请日：1985-05-21

Applicant: IBM

Inventor： KRONSTADT ERIC P ,  GHEEWALA TUSHAR R ,  GANDHI SHARAD P

IPC: G06F12/08 ,  G06F9/38

Abstract: ARCHITECTURE FOR SMALL INSTRUCTION CACHES A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18). whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction , i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table (16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.