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公开(公告)号：AT189324T
公开(公告)日：2000-02-15
申请号：AT93103645
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , HELFFRICH AUDREY ANN , ISENBERG JOHN FRANKLIN JR , MOORE BRIAN BARRY , NICK JEFFREY MARK , SWANSON MICHAEL DUSTIN , WILLIAMS JOSEPH ARTHUR
Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.
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公开(公告)号：DE69326272T2
公开(公告)日：2000-04-20
申请号：DE69326272
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , FREY JEFFREY ALAN , HELFFRICH AUDREY ANN , ISENBERG JOHN FRANKLIN , NICK JEFFREY MARK , STRICKLAND JIMMY PAUL , SWANSON MICHAEL DUSTIN , MOORE BRIAN BARRY
Abstract: A list data structure is provided within a Structured External Storage (SES) processor attached to one or more processors. Applications executing on the processors share data within the list data structure, and are provided mechanisms for conditionally executing commands at the SES. The conditional operation of complex data object operations is based upon an atomically executed predicate operation which verifies the presumed state of the data object before allowing any further data object manipulation. Modification of state information may also be atomically performed. The SES operations are initiated by a command sent as a message across the processor-SES interface.
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公开(公告)号：DE3462843D1
公开(公告)日：1987-04-30
申请号：DE3462843
申请日：1984-06-15
Applicant: IBM
Inventor： MOORE BRIAN BARRY
Abstract: In a communications system in which voice is transmitted as packets of digitized samples, a receiving station delays the output of the first packet in a way that compensates for wide variations in the intervals at which successive packets are received. According to one feature of this system, a first packet is transmitted at a higher priority so that a greater delay can be used without encounter problems that arise from the uncertainty in the delay in transmitting this packet. In another feature of this system, the arrival time of the first few packets of a conversation are detected and the delay is readjusted in case the first packet has been unusually delayed.
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公开(公告)号：DE69327679T2
公开(公告)日：2000-07-06
申请号：DE69327679
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , HELFFRICH AUDREY ANN , ISENBERG JR , MOORE BRIAN BARRY , NICK JEFFREY MARK , SWANSON MICHAEL DUSTIN , WILLIAMS JOSEPH ARTHUR
Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.
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公开(公告)号：DE1213144B
公开(公告)日：1966-03-24
申请号：DEJ0028451
申请日：1965-06-26
Applicant: IBM
Inventor： RINALDI RUSSEL GEORGE , MOORE BRIAN BARRY
Abstract: 1,070,427. Computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 28, 1965 [June 30, 1964], No. 27240/65. Heading G4A. A data processor comprises mode control means for selectively indicating when addresses in stored instructions have numeric portions only and when they have both numeric and zone portions, means for converting zone and numeric address combinations to pure numeric addresses, and instruction-responsive means operable whenever said mode control means is in its " zone and numeric " state for performing compress data handling operations. Data format.-Eight-bit characters are used, each comprising four numeric bits 1, 2, 4, 8, two zone bits A, B, a parity bit C and a word mark bit Wm. In an expanded format, one character represents one alphanumeric character, e.g. a binary-coded decimal digit. In a compressed format (used e.g. for addresses) three characters may represent five binarycoded decimal digits, by using the numeric portions to represent units, tens and hundreds digits and using the zone bits A, B of the units and hundreds characters to give the 4, 8 and 1, 2 bits of a pure binary number between 0 and 15 which can be decoded (Fig. 18, not shown) to give binary-coded thousands and ten-thousands decimal digits, allowing 16,000 memory locations to be selectively addressed. Expanding data.-The numeric portions of three compressed address characters from memory can be passed in turn (in descending order) via a binary to 2/5 code converter to corresponding positions in a register AAR or BAR (Fig. 3, not shown), depending on which of the operands the address relates to, the zone portions of the units and hundreds characters being concurrently passed to a zone register (Fig. 1, not shown). Two extra cycles inserted in the ordinary instruction read-out cycle sequence (Fig. 24, not shown) are then used to pass the zone bits to a conversion circuit (Fig. 18, not shown) twice. In each cycle the 1, 2 bits go direct and the 4, 8 bit via zone adders which do not alter them, and in each cycle the conversion circuit produces binary-coded thousands and tenthousands digits which are passed to the AAR (or BAR) register (not shown) in the first and second cycles respectively. Indexing addresses.-Fifteen memory locations are used as index registers. A compressed format address may be indexed using any one of three of these. If indexing is required in compress mode, at least one of the two zone bits of the tens character is non-zero and these two zone bits constitute two bits of the four-bit register identity, the other two bits being forced ones (Fig. 39, not shown). The address to be indexed is expanded as in "Expand data" above but the expanded address is placed in a register CAR (or DAR) as well as in AAR (or BAR) (Fig. 3, not shown), and the tens zone bits are used to select the index register. The latter stores a three-character compressed increment which is added as follows to the contents of the CAR (or DAR), the result being stored in the AAR (or BAR), during five extra cycles inserted in the instruction read-out cycle sequence (Fig. 24, not shown). The thousands ten-thousands (2 out of 5 coded) decimal digits in the CAR (or DAR) are converted to a single 4-bit binary member the 4 and 8 bits of which are added to the zone bits of the units character from the index register, the result being stored in the 4, 8 bit positions of the zone register. The units digit from CAR (or DAR) is added to the numeric portion of the units indexing character, any carry being saved for the tens addition to follow. Tens and hundreds additions then take place similarly, no zone additions taking place in the tens and those in the hundreds (adding the 1, 2 bits from the thousands and tenthousands CAR or DAR characters to the hundreds indexing zones) providing 1, 2 bits to be stored in the zone register. Any carry from the numeric hundreds addition is incorporated in the 1, 2 zones addition taking place concurrently. Any carry from this zones addition sets a carry latch. The zone register contents are then applied to the conversion circuit mentioned twice in respective cycles, the 1, 2 bits direct and the 4, 8 bits via the zone adders, the carry which set the latch (see above) being added in. The conversion circuit produces thousands and ten-thousands binary-coded decimal digits which are passed to the AAR (or BAR) in the two cycles respectively, being converted to 2/5 coded form on the way. Compressing data.-A five-character expanded address in the BAR may be converted to a three-character compressed address and stored in a memory address specified by the AAR, in the now obvious fashion. Adding two compressed operands.-The units characters of the two operands are read from memory in turn, the zone and numeric portions of the first being stored in the zone register and a Y register (Fig. 2, not shown) respectively until the units character of the second operand is available. The numeric portions and zone portions are then added separately and the results returned to one of the operand locations in memory. Any numeric carry is saved for the tens numeric addition to follow. The tens and hundreds characters are then treated similarly, numeric carries being propagated to the next numeric addition, except that no zone addition takes place with the tens, and any hundreds numeric carry is incorporated in the hundreds zones addition. Any hundreds zones carry sets a latch and necessitates an extra cycle in which the units (result) character is removed from memory and has the carry added to its zone portion. General.-The system is described as a modification of that of Specification 1,070,423 which is referred to. Modifications to format mentioned.-Each character could have four zone bits, or the four zone bits required for the thousands and tenthousands order could come one from each of four characters. Alternatively, the carry from the zone bits (4, 8) of the unit character above could, instead of being ignored, be applied to the low-order numerics of another character set. Also the tens order zones could be used in combination with the units and hundreds zones to represent a binary member.
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Patent Agency Ranking
公开(公告)号：DE2361401A1
公开(公告)日：1974-07-18
申请号：DE2361401
申请日：1973-12-10
Applicant: IBM
Inventor： MOORE BRIAN BARRY , THORN CARYL ALLWYN
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公开(公告)号：DE2362916A1
公开(公告)日：1974-07-04
申请号：DE2362916
申请日：1973-12-18
Applicant: IBM
Inventor： BROADHURST DENNIS , MOORE BRIAN BARRY
Abstract: 1441129 Selective signalling INTERNATIONAL BUSINESS MACHINES CORP 26 Nov 1973 [29 Dec 1972] 54762/73 Heading G4H [Also in Division H4] In a multiple-unit communication system, each of a plurality of the units is capable of receiving data and includes a frame generator and a frame-monitor-and-data-extractor defining the start and finish of a distinct loop frame transmission path to which the remaining units have access only by way of frame processing means for inserting data into an extant frame whereby the network is receiver-driven. As disclosed, the units are the CPU and subsystems of a computer, and each unit can receive data from any of the others by way of a loop as above respective to the receiver. Transmission is serial by bit in each loop. The frame generator of a unit can generate "empty" frames up to the number of empty input buffers, and any of the other units can send information to this unit by converting one or more frames to "full" frames in their frame processing means. The frame processing means and the framemonitor-and-data-extractors synchronize on the beginnings of frames. "Idle" frames can also be sent merely to synchronize. "Full" frames are used to demand data transfer (involving reading from or writing into a store at the unit which receives the frame) or to demand control transfer, and the unit receiving either of these varieties of frame responds with an appropriate response "full" frame in the appropriate other loop. Each frame contains bits to specify its type, and the various varieties of "full" frame also contain the number of the originating unit, a demand-response correlation field, check information, and where appropriate storage protection key, data, address, byte-selecting bits, etc.
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公开(公告)号：ES2141733T3
公开(公告)日：2000-04-01
申请号：ES93103645
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , HELFFRICH AUDREY ANN , ISENBERG JOHN FRANKLIN JR , MOORE BRIAN BARRY , NICK JEFFREY MARK , SWANSON MICHAEL DUSTIN
Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.
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公开(公告)号：DE69327679D1
公开(公告)日：2000-03-02
申请号：DE69327679
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , HELFFRICH AUDREY ANN , ISENBERG JR , MOORE BRIAN BARRY , NICK JEFFREY MARK , SWANSON MICHAEL DUSTIN , WILLIAMS JOSEPH ARTHUR
Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.
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公开(公告)号：DE69326272D1
公开(公告)日：1999-10-14
申请号：DE69326272
申请日：1993-03-08
Applicant: IBM
Inventor： ELKO DAVID ARLEN , FREY JEFFREY ALAN , HELFFRICH AUDREY ANN , ISENBERG JOHN FRANKLIN , NICK JEFFREY MARK , STRICKLAND JIMMY PAUL , SWANSON MICHAEL DUSTIN , MOORE BRIAN BARRY
Abstract: A list data structure is provided within a Structured External Storage (SES) processor attached to one or more processors. Applications executing on the processors share data within the list data structure, and are provided mechanisms for conditionally executing commands at the SES. The conditional operation of complex data object operations is based upon an atomically executed predicate operation which verifies the presumed state of the data object before allowing any further data object manipulation. Modification of state information may also be atomically performed. The SES operations are initiated by a command sent as a message across the processor-SES interface.
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