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    1.
    发明专利
    未知

    公开(公告)号：AT189324T

    公开(公告)日：2000-02-15

    申请号：AT93103645

    申请日：1993-03-08

    Applicant: IBM

    Inventor： ELKO DAVID ARLEN ,  HELFFRICH AUDREY ANN ,  ISENBERG JOHN FRANKLIN JR ,  MOORE BRIAN BARRY ,  NICK JEFFREY MARK ,  SWANSON MICHAEL DUSTIN ,  WILLIAMS JOSEPH ARTHUR

    IPC: G06F13/00 ,  G06F13/12 ,  G06F15/17 ,  G06F15/173 ,  G06F15/16 ,  G06F12/08

    Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.

    3.
    发明专利
    未知

    公开(公告)号：DE69327679T2

    公开(公告)日：2000-07-06

    申请号：DE69327679

    申请日：1993-03-08

    Applicant: IBM

    Inventor： ELKO DAVID ARLEN ,  HELFFRICH AUDREY ANN ,  ISENBERG JR ,  MOORE BRIAN BARRY ,  NICK JEFFREY MARK ,  SWANSON MICHAEL DUSTIN ,  WILLIAMS JOSEPH ARTHUR

    IPC: G06F13/00 ,  G06F13/12 ,  G06F15/17 ,  G06F15/173 ,  G06F15/16 ,  G06F12/08

    Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.

    SYSTEM INPUT/OUTPUT INTERFACE DESIGN FOR SCALING.
    4.
    发明专利
    SYSTEM INPUT/OUTPUT INTERFACE DESIGN FOR SCALING. 未知

    公开(公告)号：MY122111A

    公开(公告)日：2006-03-31

    申请号：MYPI9803080

    申请日：1998-07-07

    Applicant: IBM

    Inventor： BEUKEMA BRUCE LEROY ,  BUCKLAND PATRICK ALLEN ,  CHEN WEN-TZER THOMAS ,  ELKO DAVID ARLEN ,  JUDD IAN DAVID ,  RECIO RENATO JOHN

    IPC: G06F13/28 ,  G06F3/00 ,  G06F9/06 ,  G06F12/08

    Abstract: THE SYSTEM I/O INTERFACE (24) AND ITS DATA STRUCTURE (26) ARE DESIGNED TO MINIMIZE THE HOST CPU UTILIZATION IN DRIVING AN ADAPTER (18, 20). THE INTERFACE IS ALSO DESIGNED TO REDUCE THE SYSTEM INTERFERENCE IN PROCESSING I/O REQUESTS. TO ELIMINATE THE NEED OF USING PIO INSTRUCTIONS, THE COMMAND/STATUS BLOCKS FOR EXCHANGING MESSAGES BETWEEN THE SYSTEM (10) AND THE ADAPTER RESIDE IN THE SYSTEM MEMORY (14). THE DATA STRUCTURE IS DESIGNED TO AVOID "SHARE WRITE" ENTRIES IN ORDER TO FURTHER MINIMIZE THE OVERHEAD OF MAINTAINING EACH COHERENCY WHEN UPDATING AN ENTRY IN THE CACHE EITHER CONCURRENTLY OR SEQUENTIALLY BY BOTH ADAPTER AND SYSTEM CPU (12). FURTHER, THE DATA STRUCTURE OF THE CONTROL AND STATUS BLOCKS IS RESIDED IN THE SYSTEM MEMORY. THE SYSTEM CPU USES STORE INSTRUCTION TO PREPARE CONTROL BLOCKS AND LOAD INSTRUCTION TO READ FROM COMPLETION STATUS BLOCKS; WHILE THE ADAPTER WILL RELY ON ITS DMA ENGINE TO MOVE DATA TO/FROM SYSTEM MEMORY IN ACCESSING CONTROL/STATUS BLOCKS.(FIG. 1)

    6.
    发明专利
    未知

    公开(公告)号：AT343277T

    公开(公告)日：2006-11-15

    申请号：AT04742012

    申请日：2004-08-04

    Applicant: IBM

    Inventor： ELKO DAVID ARLEN ,  LEPORE DANIEL ,  MEHTA CHETAN ,  PFISTER GREGORY FRANCIS ,  SUGRUE PATRICK JOHN

    IPC: H04L12/24

    Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an INFINIBAND distributed system-area network that includes multiple end nodes. A manager application is established in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager application. The manager application maintains a current list of active agent applications and uses the list to manage the agent applications in the end nodes.

    7.
    发明专利
    未知

    公开(公告)号：BRPI0413589A

    公开(公告)日：2006-10-17

    申请号：BRPI0413589

    申请日：2004-08-04

    Applicant: IBM

    Inventor： ELKO DAVID ARLEN ,  LEPORE DANIEL ,  MEHTA CHETAN ,  PFISTER GREGORY FRANCIS ,  SUGRUE PATRICK JOHN

    IPC: H04L12/24

    Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an INFINIBAND distributed system-area network that includes multiple end nodes. A manager application is established in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager application. The manager application maintains a current list of active agent applications and uses the list to manage the agent applications in the end nodes.

    8.
    发明专利
    未知

    公开(公告)号：AT331252T

    公开(公告)日：2006-07-15

    申请号：AT02718297

    申请日：2002-03-18

    Applicant: IBM

    Inventor： CRADDOCK DAVID ,  ELKO DAVID ARLEN ,  GREGG THOMAS ANTHONY ,  PFISTER GREGORY FRANCIS ,  RECIO RENATO JOHN

    IPC: H04L12/28 ,  G06F9/445 ,  G06F13/40

    Abstract: A method and system for a distributed computing system having components like end nodes, switches, routers and links interconnecting packets over the interconnecting links. The switches and routers interconnect the end nodes and route the packets to the appropriate end node. The end nodes reassemble the packets into a message at a destination. A mechanism is provided to allow a single physical component to appear as multiple components each with unique control levels. These components may be host channel adapters (HCAs), target channel adapters (TCAs) or switches. A method and system for end node partitioning for a physical element is provided. A configuration of the physical element is selected. A port associated with the physical element is probed, wherein the port is probed with a subnet management packet by a subnet manager. In response to detecting a switch associated with the port, a local identifier is assigned to the port resulting in a configuration change of the physical element.

    10.
    发明专利
    未知

    公开(公告)号：ES2141733T3

    公开(公告)日：2000-04-01

    申请号：ES93103645

    申请日：1993-03-08

    Applicant: IBM

    Inventor： ELKO DAVID ARLEN ,  HELFFRICH AUDREY ANN ,  ISENBERG JOHN FRANKLIN JR ,  MOORE BRIAN BARRY ,  NICK JEFFREY MARK ,  SWANSON MICHAEL DUSTIN

    IPC: G06F13/00 ,  G06F13/12 ,  G06F15/17 ,  G06F15/173 ,  G06F15/16 ,  G06F12/08

    Abstract: A mechanism for communicating messages, each including a command and a response, in a network having central processing complexes (CPCs) and one or more coupling facilities. Each coupling facility has a central processor for executing instructions and a main storage. Messages are sent from a message control block in the main storage of the CPC sending the message, and the response to the message is received in a message response block of the CPC without an interrupt to the program being executed by the central processor of the CPC. Each message from a CPC to the coupling facility may include a command and an indicator bit which instructs the coupling facility to execute the command either in synchronism with or asynchronously to the execution of the sending processor. The coupling facility executes the command and returns a response which is received in a message response block of the main storage of the sending CPC without an interrupt to any program being executed by the central processor of that CPC.

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