公开(公告)号：US3660822A

公开(公告)日：1972-05-02

申请号：US3660822D

申请日：1969-12-15

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  MOORE RICHARD L

IPC: G11C11/41 ,  G11C11/39 ,  H01L27/07 ,  H03K3/35 ,  G11C11/40 ,  H03K17/24

CPC classification number: G11C11/39 ,  G11C2211/5614 ,  H01L27/0755 ,  H01L27/0766 ,  H03K3/35 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

Abstract: This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.

Abstract translation: 本申请公开了一种使用展现负电阻工作特性的单门控多发射极半导体器件的存储单元。 半导体器件被偏置为在该负电阻特性上具有两个稳定的工作状态，并且通过连接到其发射极之一的字线和连接到另一个发射极的位线来寻址。 寄生晶体管由半导体器件的两个发射极和选通层形成。 通过对字和位线施加半选择脉冲，寄生晶体管被分解以在半导体器件的选通区域中引起临时电流流动。 当该电流在选通区域中流动时，改变半导体器件的工作特性，使半导体器件只有一个稳定的工作状态。 因此，半导体器件的操作转移到该单个操作状态。 当临时电流流动结束时，半导体器件将处于处于负电阻特性的低电压，高电流稳定状态，而与施加半选择脉冲之前的半导体器件的工作状态无关。 当这种存储单元以单体形式制造时，可获得非常高的电池密度和极高的运行速度。

公开(公告)号：US3573573A

公开(公告)日：1971-04-06

申请号：US3573573D

申请日：1968-12-23

Applicant: IBM

Inventor： MOORE RICHARD L

IPC: G11C11/411 ,  H01L27/00 ,  H01L27/07 ,  H01L29/08 ,  H01L29/8605 ,  H01L19/00

CPC classification number: H01L29/8605 ,  H01L27/00 ,  H01L27/0755 ,  H01L29/0821 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145

Abstract: This specification describes semiconductor storage cells for use in monolithic memories. These cells each have two planar transistors formed on a single surface of a monolithic chip. The planar transistors are coupled together to form a bistable circuit and are supplied power from a voltage distribution layer of the chip under the planar transistors so that the load elements for the storage cells are formed vertically through the monolithic chip between the voltage distribution layer and the planar transistors.