公开(公告)号：US3623029A

公开(公告)日：1971-11-23

申请号：US3623029D

申请日：1969-12-15

Applicant: IBM

Inventor： DAVIDSON EVAN E

IPC: G11C11/39 ,  H01L27/07 ,  H01L27/10 ,  H01L29/08 ,  H01L29/74 ,  G11C11/34 ,  G11C7/00 ,  H03K17/72

CPC classification number: G11C11/39 ,  H01L27/0744 ,  H01L27/10 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/74

Abstract: This specification discloses a storage cell which employs a single dual emitter silicon-controlled rectifying device as a storage element. This silicon-controlled rectifier device is biased to have two stable-operating states and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A transistor is formed by these two emitters and the gating layer of the silicon-controlled rectifier. By application of half select pulses to the word and bit lines this transistor is broken down so as to cause current to flow in the gating region or layer of the silicon-controlled rectifier. When current flows in the gating region the operating characteristic of the silicon-controlled rectifier changes so that the silicon-controlled rectifier switches from a highvoltage, low-current stable state to a low-voltage, high-current stable state along the operating curve of the silicon-controlled rectifier. To increase the turnoff speed of the silicon-controlled rectifier a Schottky Barrier diode is connected between the gating layer and the other intermediate layer of the siliconcontrolled rectifying device to discharge charge stored in the junction between the two layers.

公开(公告)号：US3660822A

公开(公告)日：1972-05-02

申请号：US3660822D

申请日：1969-12-15

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  MOORE RICHARD L

IPC: G11C11/41 ,  G11C11/39 ,  H01L27/07 ,  H03K3/35 ,  G11C11/40 ,  H03K17/24

CPC classification number: G11C11/39 ,  G11C2211/5614 ,  H01L27/0755 ,  H01L27/0766 ,  H03K3/35 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

Abstract: This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.

Abstract translation: 本申请公开了一种使用展现负电阻工作特性的单门控多发射极半导体器件的存储单元。 半导体器件被偏置为在该负电阻特性上具有两个稳定的工作状态，并且通过连接到其发射极之一的字线和连接到另一个发射极的位线来寻址。 寄生晶体管由半导体器件的两个发射极和选通层形成。 通过对字和位线施加半选择脉冲，寄生晶体管被分解以在半导体器件的选通区域中引起临时电流流动。 当该电流在选通区域中流动时，改变半导体器件的工作特性，使半导体器件只有一个稳定的工作状态。 因此，半导体器件的操作转移到该单个操作状态。 当临时电流流动结束时，半导体器件将处于处于负电阻特性的低电压，高电流稳定状态，而与施加半选择脉冲之前的半导体器件的工作状态无关。 当这种存储单元以单体形式制造时，可获得非常高的电池密度和极高的运行速度。

公开(公告)号：JPS6291873A

公开(公告)日：1987-04-27

申请号：JP18026286

申请日：1986-08-01

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  KIESLING DAVID A

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/316 ,  G01R31/319 ,  H01L21/822 ,  H01L27/04

公开(公告)号：DE2526477A1

公开(公告)日：1976-01-15

申请号：DE2526477

申请日：1975-06-13

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  LANE RALPH D

IPC: H01P1/24 ,  H01L21/822 ,  H01L27/04 ,  H03H7/38 ,  H04B3/02 ,  H04B3/40

公开(公告)号：FR2276742A1

公开(公告)日：1976-01-23

申请号：FR7515096

申请日：1975-05-06

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  LANE RALPH D

IPC: H01P1/24 ,  H01L21/822 ,  H01L27/04 ,  H03H7/38 ,  H04B3/02 ,  H04B3/40 ,  H04B3/04

公开(公告)号：CA981365A

公开(公告)日：1976-01-06

申请号：CA163470

申请日：1973-02-08

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  LANE RALPH D ,  SAIA JERRY

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02

Abstract: 1367058 Capacitive memory cells INTERNATIONAL BUSINESS MACHINES CORP 1 Feb 1973 [20 March 1972] 5028/73 Heading H3T A capacitor data storage cell CS is refreshed during a read operation by a latch circuit 9. Data is read from CS by a F.E.T. Q1 in response to a low voltage on the word line 4. If a high level (1) is stored, a transistor 7 conducts to raise the bit line 5, and this triggers the latch 9 which is an SCR in Fig. 1. The latch acts to raise the voltage on line 5 above that which was necessary to initiate triggering, and this raised voltage is fed through another transistor 6 to refresh the storage cell CS. The capacitance of the line 5 is discharged by a transistor 12 which is turned on at the beginning of a read operation, but turned off before the word line 4 voltage is lowered to effect reading. Transistors 12 and Q1 are turned on together, however, if it is desired to write a "0" (i.e. CS is earthed). To write a "1" a further transistor 13 is turned on to raise bit line 5 to +V while word line 4 turns on Q1. Instead of the SCR 9, an emitter coupled pair (16, 17, Fig. 2, not shown) with a positive feedback emitter follower 20, may be used; this has to be reset by a transistor inverter 25. The collector load in the emitter coupled pair may be either a resistor, or (Fig. 3, not shown) a F.E.T. (31) with a gate-source capacitor which is precharged by a further F.E.T. 29 and which boosts conduction of the load F.E.T. (31). The load F.E.T. (31) is fed with a pulsed power supply which is high during a read (refresh) operation, but goes low thereafter and resets the latch by way of the feedback transistor (30).

公开(公告)号：DE3686989T2

公开(公告)日：1993-04-22

申请号：DE3686989

申请日：1986-08-08

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  KIESLING DAVID A

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/316 ,  G01R31/319 ,  H01L21/822 ,  H01L27/04 ,  G06F11/26

Abstract: A test system having improved means for reducing driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit device, such as a logic chip. The integrated circuit device has a plurality of input terminals (R5-R54) for receiving an electrical test pattern from the tester. The integrated circuit device also includes a plurality of output driver circuits (D2-D1O2) having outputs connected to the tester. The test system is characterized in that said integrated circuit device includes a driver sequencing circuit (L1-L1O) responsive to at least one control signal (R1-R4) from said tester to sequentially condition said driver circuits for possible switching, whereby delta I noise is reduced during testing.

公开(公告)号：DE3686989D1

公开(公告)日：1992-11-26

申请号：DE3686989

申请日：1986-08-08

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  KIESLING DAVID A

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/316 ,  G01R31/319 ,  H01L21/822 ,  H01L27/04 ,  G06F11/26

Abstract: A test system having improved means for reducing driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit device, such as a logic chip. The integrated circuit device has a plurality of input terminals (R5-R54) for receiving an electrical test pattern from the tester. The integrated circuit device also includes a plurality of output driver circuits (D2-D1O2) having outputs connected to the tester. The test system is characterized in that said integrated circuit device includes a driver sequencing circuit (L1-L1O) responsive to at least one control signal (R1-R4) from said tester to sequentially condition said driver circuits for possible switching, whereby delta I noise is reduced during testing.