公开(公告)号：DE69120816D1

公开(公告)日：1996-08-14

申请号：DE69120816

申请日：1991-09-26

Applicant: IBM

Inventor： BORGNIS PHILIPPE ,  CRESP JACQUES ,  MOREAU ROBERT

IPC: H04L7/00 ,  H04J3/12 ,  H04J3/14 ,  H04L7/08 ,  H04L29/10 ,  H04Q11/04

Abstract: A frame transfer mechanism for a processor controlled network node connected to network link wherein fixed-length data frames including a fixed number of slots are to be transferred to and from memory 10 under processor 23 control. The incoming data flow through a FIFO-IN shift register 22. The outgoing frames flow through a FIFO-OUT 24 register. Both FIFO's are provided with an extra bit position. Said extra-bit is used to insert a synchronization-bit (flag) used to control synchronization operation of the system. The extra-bit position is fedback from FIFO-OUT to FIFO-IN to enable wrap-test operation.