1.
    发明专利
    未知

    公开(公告)号:DE69825366T2

    公开(公告)日:2005-08-18

    申请号:DE69825366

    申请日:1998-04-30

    Applicant: IBM

    Abstract: The connecting device includes a securing plate and locking spring attached to the cable connector of the cable-to-card connectors. The connecting device is pressed, when the connectors are mated, by the front portion of the cable connector against the host machine chassis which in turn is pressed flat against the adapter card brackets. In a preferred embodiment the connecting device is attached on the front portion of a standard cable connector with removable fastener, in particular with a locking spring. In another embodiment, the connecting device is an integral part of the cable connector.

    2.
    发明专利
    未知

    公开(公告)号:DE69825366D1

    公开(公告)日:2004-09-09

    申请号:DE69825366

    申请日:1998-04-30

    Applicant: IBM

    Abstract: The connecting device includes a securing plate and locking spring attached to the cable connector of the cable-to-card connectors. The connecting device is pressed, when the connectors are mated, by the front portion of the cable connector against the host machine chassis which in turn is pressed flat against the adapter card brackets. In a preferred embodiment the connecting device is attached on the front portion of a standard cable connector with removable fastener, in particular with a locking spring. In another embodiment, the connecting device is an integral part of the cable connector.

    3.
    发明专利
    未知

    公开(公告)号:DE69120816D1

    公开(公告)日:1996-08-14

    申请号:DE69120816

    申请日:1991-09-26

    Applicant: IBM

    Abstract: A frame transfer mechanism for a processor controlled network node connected to network link wherein fixed-length data frames including a fixed number of slots are to be transferred to and from memory 10 under processor 23 control. The incoming data flow through a FIFO-IN shift register 22. The outgoing frames flow through a FIFO-OUT 24 register. Both FIFO's are provided with an extra bit position. Said extra-bit is used to insert a synchronization-bit (flag) used to control synchronization operation of the system. The extra-bit position is fedback from FIFO-OUT to FIFO-IN to enable wrap-test operation.

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