公开(公告)号：JP2002335166A

公开(公告)日：2002-11-22

申请号：JP2001196145

申请日：2001-06-28

Applicant: IBM

Inventor： YAMANE TOSHIYUKI ,  KATAYAMA YASUNAO ,  MORIOKA SUMIO

IPC: G06F11/10 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a signal processing method, a signal processing system, a program for the signal processing, and a computer-connectable recording medium for recording the processing program. SOLUTION: The signal processing method for the digital signal includes a step of formulating a Yule-Walker equations in a prescribed form of a matrix of elements in a Galois field (2 ) and a vector, including the element as a factor in the Galois field (2 ), a step of returning the solution of the equation to a calculation of a symmetric matrix in a Jacobi's formula, a step of determining the number of errors as the size of the maximum matrix corresponding to the solution other than zero, and a step of determining whether or not the number of errors is equal to the maximum number of correctable errors.

公开(公告)号：JP2002335165A

公开(公告)日：2002-11-22

申请号：JP2001196027

申请日：2001-06-28

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO ,  YAMANE TOSHIYUKI

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/37

Abstract: PROBLEM TO BE SOLVED: To provide a combinational circuit, an encoder by using the combinational circuit, a decoder, and a semiconductor device. SOLUTION: The combinational circuit includes a plurality of multipliers, for multiplying individually two or more encoded digital signals in a Galois field GF (2 ), where (m) is an integer of 2 or larger. The multiplier is composed of an input-side XOR processor, an AND processor and an output-side XOR processor, and the input-side XOR processor functions in common, for the plurality of multipliers. The multiplier includes an adder connected between the AND processor and the output-side XOR processor, and the output-side XOR processor is used in common. The output from the AND processors of the multipliers are added by the adder, and the added result can be processed by the common output-side XOR processor.

公开(公告)号：JP2003223100A

公开(公告)日：2003-08-08

申请号：JP2002017959

申请日：2002-01-28

Applicant: IBM

Inventor： MORIOKA SUMIO ,  SATO AKASHI ,  CHO KO

IPC: G06F17/50 ,  G09C1/00 ,  H03K19/0952 ,  H03K19/20 ,  H04L9/06

Abstract: PROBLEM TO BE SOLVED: To provide a technique for realizing a high speed combinational circuit including an S-Box and for simultaneously generating an RO-BDD prescribing the circuit structure of the combinational circuit. SOLUTION: The combinational circuit is provided with the number of independent selector groups 100 to 170 corresponding to the number of output bits that individually generates the output bits and a driver chain that supplies primary input to the respective selector groups 100 to 170, the respective selector groups 100 to 170 are provided with a plurality of selectors 101 connected by forming the number of stages equal to or less than the number of bits of the primary input and selected signals of the selectors 101 at the respective stages are driven by one primary input. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002335167A

公开(公告)日：2002-11-22

申请号：JP2001196223

申请日：2001-06-28

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  MORIOKA SUMIO ,  YAMANE TOSHIYUKI

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/27 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To provide a decoding circuit, a decoder with the decoding circuit, a decoding method, and a semiconductor device. SOLUTION: The decoding circuit for correcting an error in digital signal is composed of an input unit 10 for receiving an input digital encoded signal ID in parallel corresponding to code interleaving; a processing unit 12, including an error-position polynomial coefficient processing unit 18 and an error-value polynomial coefficient processing unit 20 for processing each data output in serial among interleaved encoded words from the input unit 10; and an output unit 14 for receiving the output of the processing unit 12 and the input digital signal ID, and generating an output digital signal OD, in parallel corresponding to the code interleaving, after the error is corrected in a linear processing in the Galois field from the output of processing unit 12 and the input digital signal.

公开(公告)号：JP2000307435A

公开(公告)日：2000-11-02

申请号：JP9864799

申请日：1999-04-06

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To reduce the overall circuit scale by allowing a plurality of coding circuits having different maximum error correction capability to share most of circuit components in common. SOLUTION: In the case that a received message is an information word, an attachment circuit 10 attaches a fixed value to the information word. Then a linear arithmetic circuit 11 receives data resulting from attaching the fixed value to this information word, or data of the received message when it is a received word, or data resulting from adding a prescribed fixed value to a received word, if required, to make number of bits of the data given to the linear arithmetic circuit constant, and applies a linear arithmetic operation to the received data by using a prescribed matrix to calculate an intermediate signal (u). The bit length of the intermediate signal (u) is smaller than that of a corrected word given to the linear arithmetic circuit 11. That is, number of circuits can remarkably be reduced by using the intermediate signal (u) with the smaller bit length so as to obtain a parity value or the like without using the information word and the received word that are directly received for the parity calculation and the syndrome calculation.

公开(公告)号：JP2005157832A

公开(公告)日：2005-06-16

申请号：JP2003396872

申请日：2003-11-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KUBO HIROAKI ,  MORIOKA SUMIO ,  CHO AMI

IPC: G06F17/14 ,  H04N19/60 ,  H04N19/625 ,  H04N7/30

Abstract: PROBLEM TO BE SOLVED: To provide a method of an inverse discrete cosine transform (IDCT) for reproducing a compressed image with high fidelity by limiting an accumulation of round-off errors of the decimal point arithmetic.
SOLUTION: The method of the inverse discrete cosine transform includes a step for receiving a temporary data t'(k, v) with 30 bits as a result of executing a one dimensional inverse discrete cosine transform, a mode 0 step for reserving a memory for 11 bits (without including a sign bit S) for use of an integer when the temporary data is stored in an external RAM if the integer of the data t'(k, v) is not within a range of -128 to +127, and a mode 1 step, which, on the other hand, reserves 7 bits (without including a sign bit S) for the integer if the integer is within the range of -128 to +127 and allocates remaining 4 bits to the decimals. Consequently, the method can increase the accuracy of computing the data t'(k, v) without expanding the external RAM required for temporally storing the data t'(k, v).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于通过限制小数点算术的舍入误差的积累来以高保真度再现压缩图像的逆离散余弦变换（IDCT）的方法。 解决方案：逆离散余弦变换的方法包括作为执行一维逆离散余弦变换的结果，接收具有30位的临时数据t'（k，v）的步骤，用于保留的模式0步骤 如果数据t'（k，v）的整数不在-128到...的范围内，当临时数据存储在外部RAM中时，用于11位（不包括符号位S）的存储器用于整数 +127，另一方面，如果整数在-128至+127的范围内，则为整数保留7位（不包括符号位S），并将剩余的4位分配给 小数点。 因此，该方法可以提高计算数据t'（k，v）的精度，而不会扩展临时存储数据t'（k，v）所需的外部RAM。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002023999A

公开(公告)日：2002-01-25

申请号：JP2000185582

申请日：2000-06-21

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO

IPC: G06F7/552 ,  G06F7/72 ,  G09C1/00 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a multiplication module for multiplying m-bit data on a Galois field GF (2m) (m>=1). SOLUTION: This multiplication module is provided with 1st and 2nd power exponent computing means u1 and u2 to which 1st m-bit data is inputted from a 1st input part, a 1st multiplying means u3 to which the 1st m-bit data and an output from the 1st power exponent computing mean are inputted, a 2nd multiplying means u4 to which 2nd m-bit data from a 2nd input part and an output from the means u2 are inputted and a selecting means u5 to which an output signal of a the 2nd multiplying means and the 2nd m-bit data are inputted. A 1st control signal S1 is inputted to the 1st power exponent computing means, a 2nd control signal S2 is inputted to the 2nd power exponent computing means, a 3rd control signal S0 for controlling the output of the selecting means is inputted to the selecting means, the 1st multiplying means outputs a 1st output signal, and the selecting means outputs a 2nd output signal.

公开(公告)号：JP2000114984A

公开(公告)日：2000-04-21

申请号：JP26849398

申请日：1998-09-22

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  MORIOKA SUMIO

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a decoding circuit for a Reed-Solomon code which is fast and low power consumption. SOLUTION: A syndrome calculating circuit 1 calculates a syndrome Sj (j=0, 1,..., 2t-1) from a 1st codeword Yi (i=0, 1,..., n-1) that may include an error. A coefficient calculating circuit 3 calculates the coefficient Λk of an error position polynomial corresponding to the number of estimated errors (e) (e

公开(公告)号：JP2004201038A

公开(公告)日：2004-07-15

申请号：JP2002367334

申请日：2002-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SATO AKASHI ,  MORIOKA SUMIO ,  TAKANO KOJI

IPC: G06F12/14 ,  G06F21/00 ,  G06F21/02 ,  G06F21/24 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F21/80 ,  H04L9/0822 ,  H04L9/14 ,  H04L9/3226 ,  H04L2209/60

Abstract: PROBLEM TO BE SOLVED: To provide a technology for the encryption processing of stored data and the management of an encryption key suitably applicable to the case that the user authentication and encryption of stored data are both applied to a storage device. SOLUTION: The storage device is provided with an encryption circuit 54 for using an encryption key created from prescribed individual identification information such as a password to encrypt desired data and the individual identification information itself, a magnetic disk 10 for recording the data and the individual identification information encrypted by the encryption circuit 54, and a CPU 58 for using the encrypted individual identification information stored in the magnetic disk 10 to authenticate a user. Then the storage device authenticates the user on the basis of authentication data, uses the encryption key to encrypt write data transmitted from a host system and records the encrypted data to the magnetic disk 10, or uses the encryption key to decrypt the data read from the magnetic disk 10 and to transmit the decrypted data to the host system. COPYRIGHT: (C)2004,JPO&NCIPI