公开(公告)号：JPH05289868A

公开(公告)日：1993-11-05

申请号：JP3484292

申请日：1992-02-21

Applicant: IBM

Inventor： KONO SEIICHI ,  KOMIYAMA HIROHIDE ,  MUKOYAMA SHUICHI

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: PURPOSE: To perform normal switching by prereading an instruction, which will be executed following an instruction for address generation mode switching, to hold it in a prefetch queue at the time of executing the instruction for address generation mode switching. CONSTITUTION: JMP +2 is executed to flash a prefetch queue 2A, and contents of a DRO register are temporarily transferred to an EDX register and are returned to the DRO register by execution of MOV DRO and EDX. An instruction prefetch unit 2 prereads an instruction to store it in a prefetch queue 2A in the middle or execution or these instructions MOV DRO and EDX. Since the instruction (JMP offset value, selector value)to be executed following instructions MOV CRO and EAX for mode switching is fetched in a prefetch queue 2A, the system is prevented from being hung or malfunctioning because of transfer of the control to an erroneous address just after mode switching.