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公开(公告)号：JP2003017709A
公开(公告)日：2003-01-17
申请号：JP2002123022
申请日：2002-04-24
Inventor： ASSADERAGHI FARIBORZ , CHEN TZE-CHIANG , MULLER PAUL K , EDWARD J NOWAKU , SHAHIDI GHAVAM G
IPC: H01L21/28 , H01L21/336 , H01L29/41 , H01L29/78 , H01L29/786
CPC classification number: H01L29/66757 , H01L29/66772 , H01L29/78618 , H01L29/78651 , H01L29/78675
Abstract: PROBLEM TO BE SOLVED: To provide a design capable of manufacturing a field-effect transistor which is fine in size and contains a sub-lithography channel length on an SOI wafer or a chip with a high degree of integration through a well-known and fully-developed process. SOLUTION: A short channel effect can be effectively restrained by the use of the impurity concentration of a steep gradient which can be accurately improved in shape and arranged at a proper position, and on the other hand, impurities are injected into a polysilicon seed adjacent to the conduction channel of a transistor and diffused into the conduction channel from the polysilicon seed to relax the allowance of a process. The polysilicon seed enables a polysilicon source/drain contact, which has a structure capable of reducing its current density and path length to an irreducible minimum and giving other mechanical advantages, to grow epitaxially from the polysilicon seed.
Abstract translation: 要解决的问题：提供一种能够制造尺寸精细并且在SOI晶片或具有高度集成度的芯片上的亚光刻通道长度通过公知的和完全的集成的场效应晶体管的设计 开发过程。 解决方案：通过使用可以精确改善形状并排列在适当位置的陡峭梯度的杂质浓度，可以有效地抑制短通道效应，另一方面，将杂质注入邻近的多晶硅晶种 晶体管的导电沟道，并且从多晶硅晶种扩散到导电沟道中以放宽工艺的余量。 多晶硅种子能够实现多晶硅源极/漏极接触，其具有能够将其电流密度和路径长度降低到不可约最小值并提供其它机械优点的结构，以从多晶硅种子外延生长。
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公开(公告)号：JP2000205833A
公开(公告)日：2000-07-28
申请号：JP37359999
申请日：1999-12-28
Applicant: IBM , SIEMENS AG
Inventor： HALLE SCOTT D , MANTZ ULRICH , MULLER PAUL K , JAIPRAKASH VENKATACHALAM C
Abstract: PROBLEM TO BE SOLVED: To implement a practical non-destructive method for determining the depth of a recessed conductor in a trench by irradiating a substrate by an infrared light source, subjecting a reflected return signal to Fourier transformation to detect spectral contents, and correlating the spectral contents of the return signal with a logical sample spectrum. SOLUTION: In a Fourier transformation infrared(FTIR) system, controlled infrared spectrum are radiated, and the spectral contents of a return signal are detected and analyzed with Fourier analysis. A global infrared light source 20 is, for example, provided for radiating wide-band infrared energy. An interferometer is arranged in a path from the infrared light source 20 to a sample 22, comprises a movable mirror 24, a fixed mirror 26, and a beam splitter 21, and generates interference patterns which strengthen each other and interference patterns which weaken each other in a detector 25 through the use of the movable mirror 24. Then a return signal to the detector 25 from mirrors 26 and 27 is subjected to Fourier transformation, and the spectral contents of the detected return signal are correlated with a logical sample spectrum.
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公开(公告)号：JPH11260876A
公开(公告)日：1999-09-24
申请号：JP129999
申请日：1999-01-06
Applicant: IBM , SIEMENS AG
Inventor： MULLER PAUL K , JAIPRAKASH VENKATACHALAM C
IPC: G01B11/02 , G01R31/265 , H01L21/334 , H01L21/66
Abstract: PROBLEM TO BE SOLVED: To permit non-destructive measurement of a depth wherein a top part of a buried interface is positioned by irradiating a semiconductor substrate with a built-in buried interface by infrared beam, putting spectrum of returned signal to Furrier analysis, and deciding the depth of a top part of a buried interface by comparing it with spectrum. SOLUTION: A Fourier transform infrared ray system emits controlled infrared spectrum and the contents of spectrum of returned signal is detected and analyzed by Fourier analysis. An interference system generates a pattern of interference to reinforce each other and interference to weaken each other in a detector 25 by using a movable mirror 24. The pattern is decided by frequency of detected light and characteristics of a sample 22. The unknown sample 22 is irradiated by IR light, and the content of spectrum of a returned signal is analyzed to decide with which of reference or correction spectrum unknown spectrum coincides most. Reference spectrum which coincides most with unknown spectrum shows the depth of a top part of a buried plate.
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公开(公告)号：JP2001033213A
公开(公告)日：2001-02-09
申请号：JP2000173240
申请日：2000-06-09
Applicant: IBM
Inventor： GOULD CHRIS , MULLER PAUL K , PRAKASH JAI V C , VAN DEN BERG ROBERT
Abstract: PROBLEM TO BE SOLVED: To enable a simple measurement with good cost efficiency to be performed by converting the image of a repeat overlay mark into a phase image by an image processor, and analyzing the phase difference between repeat overlay marks on different levels in overlay measurement. SOLUTION: A digitizer 43 digitizes a first photo to generate a first digitized image. The digitizer 43 digitizes a second photo to generate an image. A Fourier transformer 45 transforms the second digitized image to a second geometric spectrum or a phase image. A phase comparator 48 calculates a phae difference between the first and second geometric spectra to measure alignment between two levels on a wafer 33. The digitizer 43 generates respective digitized images from a first and second portions of the photo. A signal processor 45 transforms the first and second digitized images to first and second geometric spectra. The phase comparator 48 calculates a phase difference between two geometric spectra to execute alignment measurement.
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公开(公告)号：JP2000133788A
公开(公告)日：2000-05-12
申请号：JP21479399
申请日：1999-07-29
Applicant: IBM , SIEMENS AG
Inventor： ALSMEIER JOHANN , BRONNER GARY , KAPLITA GEORGE A , KLEINHENZ RICHARD , MULLER PAUL K , RANADE RAJIV M , ROITHNER KLAUS
IPC: H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/8242 , H01L27/04 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To obviate the need for etching redesigning by laying out a deep trench pattern by using a dummy semiconductor material loading rate, that is obtained by subtracting a device trench level semiconductor material loading rate from an estimated final trench level semiconductor material loading rate. SOLUTION: First, a final chip design silicon loading rate is estimated, and a plurality of device deep trenche patterns are laid out, that constitute an integrated circuit chip 14 to be developed. These trenches cumulatively have device silicon loading rates. Next, the device silicon loading rate is subtracted from the the estimated final chip design loading rate so as to compute a dummy silicon loading rate, and cumulative silicon loading rates are used to lay out a plurality of dummy deep trenches 22. It is preferable have the device trenches disperse uniformly and the dummy trenches over a chip.
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Patent Agency Ranking
公开(公告)号：JPH10242415A
公开(公告)日：1998-09-11
申请号：JP1839798
申请日：1998-01-30
Applicant: IBM
Inventor： HALLE SCOTT D , HWANG CHORNGLII , MULLER PAUL K
IPC: H01L27/108 , H01L21/02 , H01L21/8242
Abstract: PROBLEM TO BE SOLVED: To increase the surface area of a side wall without increasing the depth of a trench by using the granular structure of polysilicon with the anisotropic etching and making the trench side wall into a rough face so that it can be controlled. SOLUTION: A trench color 6 is formed by using a thermal oxidation method and oxidized nitride is removed by isotropic etching. The isotropic etching of silicon is executed after the color oxide 6 is formed, and the rough face degree of polysilicon is improved. During etching, amorphous silicon or a polysilicon layer 4 at the lower side of the color 6 is etched into a silicon substrate 2 through the trench side wall. The side wall and the base part of the trench 1, which are at the lower side of the color oxide 6, are provided with a rough face layer as the result of etching. The trench side wall is made into the rough face by means of the granular structure of polysilicon and the preferential etching of granular boundary. Then, the rough face degree can be controlled by using isotropic etching.
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公开(公告)号：DE69837033T2
公开(公告)日：2007-08-09
申请号：DE69837033
申请日：1998-12-15
Applicant: SIEMENS AG , IBM
Inventor： MULLER PAUL K , JAIPRAKASH VENKATACHALAM C
IPC: G01B11/02 , H01L21/00 , G01B11/06 , G01N21/55 , G01R31/26 , G01R31/265 , H01L21/334 , H01L21/66
Abstract: The invention discloses a method for measuring the depth at which a buried interface below the surface in a semiconductor substrate is located in a non-destructive manner which employs Fourier Transform Infrared (FTIR) measurements. The method includes illuminating the semiconductor substrate containing the buried interface to be measured with infrared light and detecting and analyzing the spectral content of a return signal by Fourier analysis. It further involves comparing the spectral content of the return signal to calibration spectra to thereby determine the depth of the buried interface. In addition a device is also provided for measuring the depth of a buried interface.
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公开(公告)号：DE112013000899T8
公开(公告)日：2014-11-20
申请号：DE112013000899
申请日：2013-03-06
Applicant: IBM
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公开(公告)号：DE112013000899T5
公开(公告)日：2014-11-13
申请号：DE112013000899
申请日：2013-03-06
Applicant: IBM
Inventor： MULLER PAUL K , VOGEL ANDREW HAROLD , KEARNEY DANIEL JAMES , YASHCHIN EMMANUEL , LEVESQUE PAUL REJEAN
Abstract: Es wird eine automatische Steuerung oder Regelung eines mindestens eine elektronische Komponente kühlenden Kühlsystems bereitgestellt. Die Steuerung oder Regelung beinhaltet, Schwankungen einer betrieblichen Variablen des Kühlsystems oder der mindestens einen elektronischen Komponente über eine Zeitdauer zu überwachen und zumindest teilweise auf der Grundlage der Schwankungen der betrieblichen Variablen über der Zeitdauer automatisch zu ermitteln, ob die Steuerung oder Regelung des Kühlsystems anzupassen ist, um die Schwankungen der betrieblichen Variablen zu begrenzen. In einer Realisierung kann das Verfahren abhängig von den Schwankungen der betrieblichen Variablen und davon, ob die Steuerung oder Regelung des Kühlsystems zuvor angepasst wurde, weiterhin ein automatisches Ermitteln einer Ausfallwahrscheinlichkeit oder einer erwarteten Restlebensdauer des Kühlsystems, und als Reaktion darauf, dass die vorhergesagte Ausfallwahrscheinlichkeit einen ersten akzeptablen Grenzwert überschreitet oder die erwartete Restlebensdauer unter einem zweiten akzeptablen Grenzwert liegt, ein automatisches Planen einer Kühlsystem-Reparatur oder eines Kühlsystem-Austausches beinhalten.
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公开(公告)号：DE69837033D1
公开(公告)日：2007-03-22
申请号：DE69837033
申请日：1998-12-15
Applicant: SIEMENS AG , IBM
Inventor： MULLER PAUL K , JAIPRAKASH VENKATACHALAM C
IPC: G01B11/02 , H01L21/00 , G01B11/06 , G01N21/55 , G01R31/26 , G01R31/265 , H01L21/334 , H01L21/66
Abstract: The invention discloses a method for measuring the depth at which a buried interface below the surface in a semiconductor substrate is located in a non-destructive manner which employs Fourier Transform Infrared (FTIR) measurements. The method includes illuminating the semiconductor substrate containing the buried interface to be measured with infrared light and detecting and analyzing the spectral content of a return signal by Fourier analysis. It further involves comparing the spectral content of the return signal to calibration spectra to thereby determine the depth of the buried interface. In addition a device is also provided for measuring the depth of a buried interface.
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