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公开(公告)号：JP2001033213A
公开(公告)日：2001-02-09
申请号：JP2000173240
申请日：2000-06-09
Applicant: IBM
Inventor： GOULD CHRIS , MULLER PAUL K , PRAKASH JAI V C , VAN DEN BERG ROBERT
Abstract: PROBLEM TO BE SOLVED: To enable a simple measurement with good cost efficiency to be performed by converting the image of a repeat overlay mark into a phase image by an image processor, and analyzing the phase difference between repeat overlay marks on different levels in overlay measurement. SOLUTION: A digitizer 43 digitizes a first photo to generate a first digitized image. The digitizer 43 digitizes a second photo to generate an image. A Fourier transformer 45 transforms the second digitized image to a second geometric spectrum or a phase image. A phase comparator 48 calculates a phae difference between the first and second geometric spectra to measure alignment between two levels on a wafer 33. The digitizer 43 generates respective digitized images from a first and second portions of the photo. A signal processor 45 transforms the first and second digitized images to first and second geometric spectra. The phase comparator 48 calculates a phase difference between two geometric spectra to execute alignment measurement.
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公开(公告)号：JP2000243213A
公开(公告)日：2000-09-08
申请号：JP2000046289
申请日：2000-02-23
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor： WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L21/82 , H01L23/525
Abstract: PROBLEM TO BE SOLVED: To provide a method for shrinking an area for a fuse to occupy on a semiconductor tip, and to adjust a fuse resistance relative to a fuse of a semiconductor device. SOLUTION: A fuse for a semiconductor is formed, so as to have a substrate 12 having a conductive passage disposed on its surface, a dielectric layer 14 disposed on the substrate, and a vertical fuse 110 vertically disposed on the surface. The vertical fuse penetrates through the dielectric layer 14 and is connected to the conductive passage. The vertical fuse also has a hole 108, a liner material is disposed on its vertical surface, and the fuse is cut off with fusing of the liner material along the vertical surface.
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公开(公告)号：DE60034611D1
公开(公告)日：2007-06-14
申请号：DE60034611
申请日：2000-02-04
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor： WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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公开(公告)号：DE60034611T2
公开(公告)日：2008-01-31
申请号：DE60034611
申请日：2000-02-04
Applicant: QIMONDA AG , IBM
Inventor： WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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