-
公开(公告)号：JP2007058493A
公开(公告)日：2007-03-08
申请号：JP2005242148
申请日：2005-08-24
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MURAKAMI MASAHIRO
IPC: G06F9/52
CPC classification number: G06F9/526 , G06F9/3004 , G06F9/30087 , G06F12/1466
Abstract: PROBLEM TO BE SOLVED: To provide a multi-processor system for preventing load from being imposed on a processor local bus when a lock is acquired and released. SOLUTION: A lock register 22 which manages a lock is installed not at a processor local bus 18 side but at a side band bus 23 side. Then, CPU 11 to 13 perform access through the side band bus 23 to the lock register 22 when acquiring and releasing a lock. Also, when the CPU 11 to 13 output a reading signal to acquire the lock, lock bits are read from the lock register 22, and lock bits in a lock status "1" are immediately written in the lock register 22. Therefore, it is possible to perform the atomic execution of the read modify write of the lock bits. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供一种多处理器系统，用于在获取和释放锁时防止施加在处理器局部总线上的负载。 解决方案：管理锁的锁定寄存器22不是安装在处理器本地总线18侧，而是安装在边带总线23侧。 然后，当获取并释放锁时，CPU 11至13通过边带总线23执行到锁定寄存器22的访问。 此外，当CPU 11至13输出读取信号以获取锁定时，锁定位从锁定寄存器22读取，锁定状态“1”中的锁定位立即被写入锁定寄存器22中。因此，它是 可能执行读取的原子执行修改锁定位的写入。 版权所有（C）2007，JPO＆INPIT
-
公开(公告)号：JP2004179854A
公开(公告)日：2004-06-24
申请号：JP2002342268
申请日：2002-11-26
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MURAKAMI MASAHIRO , KUBO HIROAKI
IPC: H04N5/92 , H04N5/44 , H04N5/46 , H04N7/173 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/85 , H04N21/438 , H04N21/4402
CPC classification number: H04N5/4401 , H04N5/46 , H04N21/4135 , H04N21/4305 , H04N21/4334 , H04N21/434
Abstract: PROBLEM TO BE SOLVED: To provide a format conversion circuit capable of capturing the video data given from the outside by using an existing digital broadcast receiver system chip without modification.
SOLUTION: A format conversion circuit 100 is provided with: an FIFO memory 101 for writing and reading video data VD synchronously with a sampling clock CK; a header generating circuit 102 for generating a packet header of an MPEG2-TS; a synchronous timing detection circuit 103 for detecting a horizontal synchronizing signal of the video data VD; a counter 104 for counting the number of bytes of the packet header and the number of bytes of the video data VD read from the FIFO memory 101; and a switch 105 for selecting the packet header until the number of counted bytes reaches 4 bytes and thereafter selecting the video data read from the FIFO memory 101.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2010140239A
公开(公告)日：2010-06-24
申请号：JP2008315552
申请日：2008-12-11
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： ASAMOTO KENSHO , MURAKAMI MASAHIRO
IPC: G06F9/48
Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method that ensure a response within a fixed time by effectively shortening interrupt latency, which is the time from the generation of a request for interrupt handling by a device to the invocation of a handler for interrupt handling.
SOLUTION: The apparatus includes a general purpose CPU and an interrupt processor for executing an interrupt handling program for executing interrupt handling prioritized over other processing. The interrupt processor includes an interrupt handling execution unit for executing interrupt handling, a memory for storing the interrupt handling program for executing interrupt handling, an interrupt detection part for detecting an execution request requesting the execution of interrupt handling, and an interrupt handling selection part for selecting whether to execute interrupt handling on the general purpose CPU or on the interrupt handling execution unit.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：提供一种通过有效缩短中断延迟来确保在固定时间内的响应的装置和方法，这是从生成设备的中断处理请求到调用处理程序的时间 用于中断处理。 解决方案：该装置包括通用CPU和中断处理器，用于执行中断处理程序，用于执行优先于其他处理的中断处理。 中断处理器包括用于执行中断处理的中断处理执行单元，用于存储用于执行中断处理的中断处理程序的存储器，用于检测请求执行中断处理的执行请求的中断检测部分，以及用于执行中断处理选择部分的中断处理选择部分 选择是否在通用CPU或中断处理执行单元上执行中断处理。 版权所有（C）2010，JPO＆INPIT
-
公开(公告)号：JP2002112180A
公开(公告)日：2002-04-12
申请号：JP2000286931
申请日：2000-09-21
Applicant: IBM
Inventor： MURAKAMI MASAHIRO , SUGITA KATSUYUKI , KUBO HIROAKI
Abstract: PROBLEM TO BE SOLVED: To provide a digital data recording and reproducing device and its method, that records and reproduces digital data of a digital broadcast program or the like at the same time. SOLUTION: The digital data recording and reproducing device 10 is configured, such that a time division control means 18 applies time division control to a recording control means 16 and a reproduction control means 22 for recording data 42 in compliance with the MPEG2-PES(moving picture experts group phase 2-packetized elementary stream) generated by the recording control means 16 for a recording means 20 and to allow the reproduction control means 22 for read the data 42 in compliance with the MPEG2-PES recorded in the recording means 20 at the same time.
-
公开(公告)号：JP2000259554A
公开(公告)日：2000-09-22
申请号：JP6204999
申请日：1999-03-09
Applicant: IBM
Inventor： FUJITA NORIO , MURAKAMI MASAHIRO , SAKAMOTO YOSHIFUMI
IPC: G06F13/36 , G06F1/04 , G06F9/46 , G06F13/362 , G06F13/40
Abstract: PROBLEM TO BE SOLVED: To first execute other processing by interrupting a bus cycle under execution when another processing is requested on the condition that no READY signal is returned from the opposite party for a long time although a microprocessor issues a bus cycle. SOLUTION: This system uses a bridge chip 12 provided with a bus retry output part for outputting a bus retry (BRTY) signal and a microprocessor (MPU) 10 provided with a bus retry discriminating part for discriminating the presence/absence of the BRTY signal inputted from the bridge chip 12, a bus cycle control part for temporarily interrupting the bus cycle under execution and executing it again later when this bus retry discriminating part detects the input of the BRTY signal, an interrupt discriminating part for discriminating the presence/absence of another processing request when the bus cycle is interrupted and an interrupt control part for executing the other processing before the re-execution of the bus cycle when that interrupt discriminating part detects the other processing request.
-
Patent Agency Ranking
公开(公告)号：JP2012099921A
公开(公告)日：2012-05-24
申请号：JP2010244103
申请日：2010-10-29
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MAENO TAKASHI , MURAKAMI MASAHIRO
CPC classification number: G06F13/4217
Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method that can quickly transfer data between clock domains without loss or the like.SOLUTION: A circuit 100 that transfers data between a first clock domain and a second clock domain includes a data holding circuit 200 and an enable signal generation circuit 300. The enable signal generation circuit enables input and output enable signals. For first and second clocks, the input enable signal is enabled so as to cover, in a period from an edge match to the next edge match, an edge of a predetermined side of the first clock earlier than and closer to each edge of the predetermined side of the second clock appearing after the edge match, and the output enable signal is enabled so as to cover an edge of the predetermined side of the first clock later than and closer to each edge of the predetermined side of the second clock appearing after the edge match.
Abstract translation: 要解决的问题：提供可以在时钟域之间快速传输数据而不损失等的电路和方法。 解决方案：在第一时钟域和第二时钟域之间传送数据的电路100包括数据保持电路200和使能信号产生电路300.使能信号产生电路使能输入和输出使能信号。 对于第一和第二时钟，输入使能信号被使能，以便在从边缘匹配到下一个边缘匹配的时间段期间覆盖第一时钟的预定侧的早于并且更靠近预定的每个边缘的边缘 在边缘匹配之后出现的第二时钟的一侧，并且使能输出使能信号，以便覆盖第一时钟的预定侧的边缘，并且比第二时钟的预定侧的每个边缘更靠近 边缘比赛。 版权所有（C）2012，JPO＆INPIT
-
公开(公告)号：JP2002112199A
公开(公告)日：2002-04-12
申请号：JP2000273592
申请日：2000-09-08
Applicant: IBM
Inventor： KUBO HIROAKI , MURAKAMI MASAHIRO
IPC: H04N5/76 , H04L13/08 , H04N5/44 , H04N5/907 , H04N5/92 , H04N5/937 , H04N7/24 , H04N21/234 , H04N21/43 , H04N21/44 , H04N21/442
Abstract: PROBLEM TO BE SOLVED: To provide a receiving reproducing device, that can reduce the effect on reproduction of moving image data due to fluctuations in a data transmission rate produced on a communication channel. SOLUTION: The reception reproducing device 60 consists of a reception means 42, that receives moving image data transmitted via a communication channel, reproduction means 50, 52 that reproduce received moving image data, a buffer B that temporarily stores moving image data received by the reception means 42 and outputs the stored moving image data at a prescribed speed, and a buffer A that temporarily stores the moving image data outputted from the buffer B and supplies the moving image data required for the reproduction processing to the reproduction means 50, 52.
-
公开(公告)号：JP2011134162A
公开(公告)日：2011-07-07
申请号：JP2009293912
申请日：2009-12-25
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： ASAMOTO KENSHO , MURAKAMI MASAHIRO
IPC: G06F9/48
CPC classification number: G06F9/461 , G06F9/4887
Abstract: PROBLEM TO BE SOLVED: To guarantee a real-time property in multi-task control and to improve the processing efficiency of a system.
SOLUTION: The system in which a processor executes processing while switching a plurality of tasks includes: an execution means for executing an instruction of each task while switching the tasks; an identification means for identifying whether an instruction to be executed is a predetermined specific instruction; and a determination means which, when the instruction to be executed is the specific instruction, determines whether the execution means is allowed to execute the specific instruction based on a predetermined condition or to perform task switching processing without executing the specific instruction.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：保证多任务控制中的实时性，提高系统的处理效率。 解决方案：处理器在切换多个任务时执行处理的系统包括：执行装置，用于在切换任务的同时执行每个任务的指令; 识别装置，用于识别要执行的指令是否是预定的特定指令; 以及确定装置，当要执行的指令是特定指令时，确定执行装置是否被允许基于预定条件执行特定指令，或者执行任务切换处理而不执行特定指令。 版权所有（C）2011，JPO＆INPIT
-
公开(公告)号：JP2004334486A
公开(公告)日：2004-11-25
申请号：JP2003128957
申请日：2003-05-07
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： FUJITA NORIO , MURAKAMI MASAHIRO
IPC: G06F9/50 , G06F9/445 , G06F15/177
CPC classification number: G06F9/4406
Abstract: PROBLEM TO BE SOLVED: To omit a ROM for storing a boot code and maximize a cost reduction effect due to the ROM omission.
SOLUTION: A starting system 10 using boot code includes an external memory 12 storing boot code, a buffer 14 connected to the external memory 12 to accumulate the boot code transferred from the external memory 12, a DMA controller 18 for commanding the transfer of the boot code from the external memory 12 to the buffer 14, and a mapping circuit 22 connected to the buffer 14 to map the boot code accumulated in the buffer 14 to a CPU 20.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：省略用于存储引导代码的ROM，并且由于ROM省略而使成本降低效果最大化。 解决方案：使用引导代码的启动系统10包括存储引导代码的外部存储器12，连接到外部存储器12的累积从外部存储器12传送的引导代码的缓冲器14，用于命令传输的DMA控制器18 从外部存储器12到缓冲器14的引导代码以及连接到缓冲器14的映射电路22，以将累积在缓冲器14中的引导代码映射到CPU 20.版权所有：（C）2005，JPO＆NCIPI
-
公开(公告)号：JP2001144638A
公开(公告)日：2001-05-25
申请号：JP30724199
申请日：1999-10-28
Applicant: IBM
Inventor： KUBO HIROAKI , MURAKAMI MASAHIRO
Abstract: PROBLEM TO BE SOLVED: To inform a person adjusting the direction of an antenna 70 about the strength of a received signal of the antenna 70 without the need for connecting or adding a special device to the antenna 70 and a connection cable 74. SOLUTION: The satellite broadcast receiver 20 consists of a reception strength information output means 22 that outputs reception strength information denoting the strength of a received signal of the antenna 70, a modulation means 30 that multiplexes the reception strength information with a carrier, and a superimposing means 40 that superimposes the carrier with which the reception strength information is multiplexed onto the connection cable 74.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.021 seconds)
