公开(公告)号：MY104531A

公开(公告)日：1994-04-30

申请号：MYPI19902044

申请日：1990-11-20

Applicant: IBM

Inventor： TROY NEAL HICKS ,  MYHONG NGUYENPHU

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/16

Abstract: A DATA PROCESSING SYSTEM HAVING AN INSTRUCTION EXECUTION CIRCUIT THAT EXECUTES A FIRST TYPE OF INSTRUTION.ALSO INCLUDED IS A FETCH CIRCUIT THAT FETCHES INSTRUCTIONS FROM A MEMORY AND FETCHES DATA FROM THE MEMORY IN RESPONSE TO A SECOND TYPE OF INSTRUCTION. AN INSTRUCTION DECODER IS INCLUDED THAT DECODES FETCHES INSTRUCTIONS AND DISPATCHES INSTRUCTIONS OF THE FIRST TYPE TO AN INSTRUCTION QUEUEING CIRCUIT. THE INSTRUCTION DECODER FURTHER DISPATCHES INSTRUCTIONS OF THE SECOND TYPE TO THE FETCHING CIRCUIT. THE INSTRUCTION QUEUEING CIRCUIT INCLUDES THE CAPABILITY TO STORE DECODED INSTRUCTION OF THE FIRST TYPE WHILE TAGGING THESE INSTRUCTION WHEN DATA REQUIRED FOR THE EXECUTION OF THESE INSTRUCTIONS HAS NOT BEEN FETCHED.THE INSTRUCTION QUEUEING CIRCUIT FURTHER CLEARS THESE TAGS OF THESE INSTRUCTIONS OF THE FIRST TYPE WHEN DATA THAT IS REQUIRED FOR THE EXECUTION HAS BEEN FETCHED. THE INSTRUCTION QUEUEING CIRCUIT SERIALLY PROVIDES THE UNTAGGED INSTRUCTIONS OF THE FIRST TYPE TO THE INSTRUCTION EXECUTION CIRCUIT.(FIG. 3)

公开(公告)号：HK90795A

公开(公告)日：1995-06-16

申请号：HK90795

申请日：1995-06-08

Applicant: IBM

Inventor： NEAL HICKS TROY ,  MYHONG NGUYENPHU

IPC: G06F9/38 ,  G06F15/16

Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

公开(公告)号：MY105754A

公开(公告)日：1995-01-30

申请号：MYPI19891751

申请日：1989-12-13

Applicant: IBM

Inventor： JAMES ALLAN KAHLE ,  MYHONG NGUYENPHU ,  DAVID SCOTT RAY ,  GREGORY FREDERICK GROHOSKI

IPC: G06F9/38 ,  G06F1/00 ,  G06F15/16 ,  G06F9/48

Abstract: A DATA PROCESSING SYSTEM INCLUDING AN INSTRUCTION STORAGE BUFFER FOR STORING A SEQUENCE OF INSTRUCTIONS REQUIRING AN OPERATION BY AT LEAST TWO PROCESSORS. THE TWO PROCESSORS ARE PROVIDED THAT EXECUTE INSTRUCTIONS FROM THE INSTRUCTION STORAGE BUFFER. AN INSTRUCTION DISPATCH CIRCUIT IS PROVIDED THAT DISPATCHES THE INSTRUCTIONS TO THE PROCESSORS. AT LEAST ONE PROCESSOR INCLUDES THE CAPABILITY TO EXECUTE DISPATCHED INSTRUCTIONS BEFORE THE EXECUTION OF A PRECEDING INSTRUCTION N THE INSTRUCTION SEQUENCE BY ANOTHER PROCESSOR. ALSO, AT LEAST ONE PROCESSOR INCLUDES THE CAPABILITY TO DELAY EXECUTION OF AN INTERRUPTABLE INSTRUCTION UNTIL THE INSTRUCTION CAN BE EXECUTED IN ITS APPROPRIATE SEQUENTIAL ORDER IN THE SEQUENCE. ALSO, UPON THE OCCURRENCE OF THE INTERRUPT, THE PROCESSORS INCLUDE THE CAPABILITY TO PURGE THE INSTRUCTION STORAGE BUFFER IN ORDER THAT THE INTERRUPT SOFTWARE INSTRUCTIONS MAY BE STORED FOR EXECUTION.(FIG 1)

公开(公告)号：NZ236142A

公开(公告)日：1992-12-23

申请号：NZ23614290

申请日：1990-11-20

Applicant: IBM

Inventor： HICKS TROY NEAL ,  MYHONG NGUYENPHU

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/30

Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.