-
Patent Agency Ranking
公开(公告)号：AU6675390A
公开(公告)日：1991-06-27
申请号：AU6675390
申请日：1990-11-20
Applicant: IBM
Inventor： HICKS TROY NEAL , NGUYENPHU MYHONG
Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.
-
公开(公告)号：DE69017178T2
公开(公告)日：1995-08-10
申请号：DE69017178
申请日：1990-12-07
Applicant: IBM
Inventor： HICKS TROY NEAL , NGUYENPHU MYHONG
Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.
-
公开(公告)号：DE69017178D1
公开(公告)日：1995-03-30
申请号：DE69017178
申请日：1990-12-07
Applicant: IBM
Inventor： HICKS TROY NEAL , NGUYENPHU MYHONG
Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.
-
公开(公告)号：GB2322718A
公开(公告)日：1998-09-02
申请号：GB9725995
申请日：1997-12-09
Applicant: IBM
Inventor： HICKS TROY NEAL , LE HUNG OUI , MUHICH JOHN STEPHEN , WHITE STEVEN WAYNE
IPC: G06F9/38
Abstract: A pre-execution queue PEQ 42 stores instructions for an information handling system, and schedules the issuing of these instructions to at least one execution cluster 54, 56, each comprising an early, 46, 50, and a late, 48, 52, execution unit. Each execution unit executes an instruction dispatched from PEQ 42, and generates and forwards a result to another unit for execution of a further instruction. This result data forwarding takes longer if it is between units of different clusters. In particular, a result from early unit 46 is available to late unit 48 in the same cluster 54 in the same clock cycle. The instruction scheduling takes into account this non-uniform forwarding of result data (for example, by "pairing" dependent instructions and issuing them to the same cluster), and ensures that only instructions whose operands are available are scheduled. PEQ 42 classifies and groups the instructions into buckets with associated selection priorities (fig. 6). Instructions can be dynamically reassigned to buckets in response to execution delays and priority conflicts.
-
公开(公告)号：NZ236142A
公开(公告)日：1992-12-23
申请号：NZ23614290
申请日：1990-11-20
Applicant: IBM
Inventor： HICKS TROY NEAL , MYHONG NGUYENPHU
Abstract: A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.
-
-
-
-
Search Results
5
records
(took 0.018 seconds)
