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公开(公告)号：DE3270564D1
公开(公告)日：1986-05-22
申请号：DE3270564
申请日：1982-04-27
Applicant: IBM
Abstract: A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. The ROS stores frequently used sequences of microinstructions and is not altered during operation. Other sequences of microinstructions which are not frequently used are stored in the reserved portion of main storage. As required, blocks of microinstructions are paged into the WCS from the main storage. One cycle of execution is saved for each machine instruction by utilizing the operation code portion directly from the instruction register of the data processing system to access a microinstruction from the first cycle control store. An array of single-bit storage devices, accessed by microinstruction addresses also utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel. In response to a halt signal from an accessed single-bit storage device, an address substitution mechanism creates a microinstruction address which identifies a main storage location and may have to be used to initiate transfer of a block of microinstructions from main storage to the WCS to provide access to a particular substitute microinstruction for the faulty microinstruction.
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公开(公告)号：DE3274590D1
公开(公告)日：1987-01-15
申请号：DE3274590
申请日：1982-04-27
Applicant: IBM
Inventor： NADARZYNSKI EDWARD ALEXANDER , WETZEL JOSEPH ALBERT
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公开(公告)号：MX153124A
公开(公告)日：1986-08-06
申请号：MX19295682
申请日：1982-06-01
Applicant: IBM
Inventor： NADARZYNSKI EDWARD ALEXANDER , WETZEL JOSEPH ALBERT
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