公开(公告)号：JPH0644596B2

公开(公告)日：1994-06-08

申请号：JP27172885

申请日：1985-12-04

Applicant: IBM

Inventor： NAIR RAVINDRA KUMAR

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

公开(公告)号：JPS61202453A

公开(公告)日：1986-09-08

申请号：JP27172885

申请日：1985-12-04

Applicant: IBM

Inventor： NAIR RAVINDRA KUMAR

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

公开(公告)号：DE3279427D1

公开(公告)日：1989-03-09

申请号：DE3279427

申请日：1982-05-06

Applicant: IBM

Inventor： HONG SE JUNE ,  NAIR RAVINDRA KUMAR ,  SHAPIRO EUGENE

IPC: G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  G06F15/60

Abstract: The apparatus determines the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with a number of identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbour processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells. The arrangement gives reduced design times.

公开(公告)号：DE3683388D1

公开(公告)日：1992-02-27

申请号：DE3683388

申请日：1986-02-24

Applicant: IBM ,  THIOKOL MORTON INC

Inventor： NAIR RAVINDRA KUMAR

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  G06F15/60