公开(公告)号：MY104594A

公开(公告)日：1994-04-30

申请号：MYPI19901943

申请日：1990-11-05

Applicant: IBM

Inventor： ROBERT TAMLYN ,  STEVEN WILLIAM TOMASHOT ,  NATHAN RAFAEL HILTEBEITEL

IPC: G11C7/00 ,  G11C8/00 ,  G11C11/401 ,  G11C11/4096

Abstract: A DUAL-PORT DRAM IN WHICH A SINGLE SERIAL LATCH IS SHARED BETWEEN TWO PAIRS OF FOLDED BIT LINES FROM TWO ARRAYS OF MEMORY CELLS.A FIRST SET OF MUX DEVICES SELECTS ONE OF THE TWO PAIRS OF FOLDED BIT LINES FROM EACH OF THE ARRAYS, AND A SECOND SET OF MUX DEVICES SELECTIVELY COUPLE ONE OF THE REMAINING FOLDED BIT LINE PAIRS TO EITHER THE PARALLEL PORT OR THE SERIAL LATCH FOR ACCESS TO THE SERIAL PORT. THIS ARRANGEMENT GREATLY DECREASES THE CONSUMPTION OF CHIP REAL ESTATE. AT THE SAME TIME, IT MAKES UNLIMITED VERTICAL SCROLLING POSSIBLE THROUGH THE USE OF A COPY MODE THAT CAN BE CARRIED OUT IN TWO OPERATING CYCLES, AND FACILITATES MASKED WRITING, WHILE AT THE SAME TIME REDUCING CLOCKING COMPLEXITY.