公开(公告)号：JP2002324399A

公开(公告)日：2002-11-08

申请号：JP2002052065

申请日：2002-02-27

Applicant: IBM

Inventor： HOVIS WILLIAM PAUL ,  STEVEN WILLIAM TOMASHOT

IPC: G11C11/407 ,  G06F12/00 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a clocked memory device that contains programming mechanisms to set a write recovery time as a function of input clocks. SOLUTION: The clocked memory device contains programming mechanisms that permit setting the write recovery time dynamically as some function of input clocks. In one of the preferred implementations, the programming mechanisms contain a control register, which has programmable bits that can specify the write recovery time responding to their bit value. For instance, it can specify the write recovery time as a multiple of integer or fraction of clock cycles. Specifying a write recovery time as a function of clock that can be specified dynamically makes it possible to use the clocked memory device at its highest performing capability over a wide range of operating frequency.

公开(公告)号：MY104594A

公开(公告)日：1994-04-30

申请号：MYPI19901943

申请日：1990-11-05

Applicant: IBM

Inventor： ROBERT TAMLYN ,  STEVEN WILLIAM TOMASHOT ,  NATHAN RAFAEL HILTEBEITEL

IPC: G11C7/00 ,  G11C8/00 ,  G11C11/401 ,  G11C11/4096

Abstract: A DUAL-PORT DRAM IN WHICH A SINGLE SERIAL LATCH IS SHARED BETWEEN TWO PAIRS OF FOLDED BIT LINES FROM TWO ARRAYS OF MEMORY CELLS.A FIRST SET OF MUX DEVICES SELECTS ONE OF THE TWO PAIRS OF FOLDED BIT LINES FROM EACH OF THE ARRAYS, AND A SECOND SET OF MUX DEVICES SELECTIVELY COUPLE ONE OF THE REMAINING FOLDED BIT LINE PAIRS TO EITHER THE PARALLEL PORT OR THE SERIAL LATCH FOR ACCESS TO THE SERIAL PORT. THIS ARRANGEMENT GREATLY DECREASES THE CONSUMPTION OF CHIP REAL ESTATE. AT THE SAME TIME, IT MAKES UNLIMITED VERTICAL SCROLLING POSSIBLE THROUGH THE USE OF A COPY MODE THAT CAN BE CARRIED OUT IN TWO OPERATING CYCLES, AND FACILITATES MASKED WRITING, WHILE AT THE SAME TIME REDUCING CLOCKING COMPLEXITY.