公开(公告)号：EP1212675A4

公开(公告)日：2007-06-20

申请号：EP00913722

申请日：2000-03-02

Applicant: IBM

Inventor： ARMSTRONG WILLIAM JOSEPH ,  NAYAR NARESH

IPC: G06F9/00 ,  G06F9/46 ,  G06F9/50 ,  G06F9/54 ,  G06F9/40 ,  G06F13/00 ,  G06F15/16 ,  G06F15/167

CPC classification number: G06F9/542 ,  G06F9/50

Abstract: An apparatus, program product and method utilize an event-driven communications interface to support communications between multiple logical partitions (40, 42, and 44) in a logically-partitioned computer. The event-driven communications interface is at least partially disposed within a partition manager (46) that is accessible to each of the logical partitions (40, 42, and 44). Events are typically passed between logical partitions (40, 42, and 44) in the form of messages that are passed first from a source logical partition that initiates the event, through the partition manager (46), and then to a target logical partition to which the event is directed, while maintaining the independent address spaces associated with the logical partitions (40, 42, and 44).

公开(公告)号：WO03019360A2

公开(公告)日：2003-03-06

申请号：PCT/EP0208233

申请日：2002-07-24

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： ARMSTRONG WILLIAM JOSEPH ,  FRANCOIS CHRIS ,  NAYAR NARESH

IPC: G06F9/46 ,  G06F9/00 ,  G06F9/44 ,  G06F9/48 ,  G06F9/50 ,  G06F15/00

CPC classification number: G06F9/4843 ,  G06F9/4881 ,  G06F9/5077

Abstract: An apparatus, program product and method for coordinating the distribution of CPUs as among logically-partitioned virtual processors. A virtual processor may yield a CPU to precipitate an occurrence upon which its own execution may be predicated. As such, program code may dispatch the surrendered CPU to a designated virtual processor.

Abstract translation: 一种用于在逻辑分区的虚拟处理器之间协调CPU分配的装置，程序产品和方法。 虚拟处理器可能会产生一个CPU来产生一个预测其自身执行的事件。 这样，程序代码可以将交出的CPU分派给指定的虚拟处理器。

公开(公告)号：WO2013102532A3

公开(公告)日：2013-08-29

申请号：PCT/EP2012074935

申请日：2012-12-10

Applicant: IBM ,  IBM UK

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455 ,  G06F9/38

CPC classification number: G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract translation: 用于在多个逻辑分区（LPAR）中模拟独占使用处理器核心的技术包括响应于LPAR的访问请求而提供硬件线程相关状态信息，所述访问请求反映了LPAR访问硬件线程相关的专用处理器 信息。 如果请求者是在低于管理程序特权级别的特权级别上执行的程序，则响应于访问请求而返回的信息被变换，使得每个逻辑分区都像处理器独占使用那样查看处理器。 该技术可以由处理器内核中的逻辑电路块来实现，该逻辑电路块将硬件线程特定信息变换成硬件线程特定信息的逻辑表示，或者该变换可以由中断处理程序的程序指令执行， 包含信息的物理寄存器。

公开(公告)号：WO2006117394A2

公开(公告)日：2006-11-09

申请号：PCT/EP2006062046

申请日：2006-05-04

Applicant: IBM ,  IBM UK ,  ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

Inventor： ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

IPC: G06F12/10

CPC classification number: G06F3/065 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/109

Abstract: Managing computer memory in a computer with dynamic logical partitioning that operates transparently with respect to operating systems in logical partitions. Exemplary methods, systems, and products are described for managing computer memory in a computer with dynamic logical partitioning that include copying by a hypervisor, from page frames in one logical memory block ("LMB") of a logical partition ("LPAR") to page frames outside the LMB, contents of page frames having page frame numbers in a page table for an operating system in the LPAR. Embodiments typically include storing new page frame numbers in the page table, including storing by the hypervisor, for each page frame whose contents are copied, a new page frame number that identifies the page frame to which contents are copied. In typical embodiments, copying contents of page frames and storing new page frame numbers are carried out transparently with respect to the operating system.

Abstract translation: 在具有相对于逻辑分区中的操作系统透明运行的动态逻辑分区的计算机中管理计算机内存。 描述了用于在具有动态逻辑划分的计算机中管理计算机存储器的示例性方法，系统和产品，其包括由管理程序从逻辑分区（“LPAR”）的一个逻辑存储块（“LMB”）中的页面帧到 在LMB之外的页框，在LPAR中的操作系统的页表中具有页框号的页框内容。 实施例通常包括在页面表中存储新的页面帧号码，包括由管理程序存储针对其内容被复制的每个页面帧的新的页面帧号码，其标识内容被复制到的页面帧。 在典型的实施例中，相对于操作系统透明地执行复印页面的内容和存储新的页面帧号码。

公开(公告)号：EP1390839A4

公开(公告)日：2007-12-12

申请号：EP01995451

申请日：2001-12-11

Applicant: IBM

Inventor： ARMSTRONG WILLIAM J ,  MANGES MARK GREGORY ,  NAYAR NARESH ,  SCHELL JEFFREY JAY ,  WILCOX CRAIG ALDEN

IPC: G06F9/50

CPC classification number: G06F9/5077 ,  G06F2209/5012

Abstract: A processor allocation mechanism for a logically partitionable computer system allows an administrator to specify processing capability allocable to each partition as an equivalent number of processors (401), where the processing capability may be specified as a non-integer value. This processing capability value is unaffected by changes to the processing capability values of other partitions. The administrator may designate multiple sets of processors (402), assigning each physical processor of the system to a respective processor set (403). Each logical partition is constrained to execute in an assigned processor set (404), which may be shared by more than one partition. Preferably, the administrator may designate a logical partition as either capped, meaning that a partition can not use excess idle capacity of the processors, or uncapped, meaning that it can.

公开(公告)号：JP2006127524A

公开(公告)日：2006-05-18

申请号：JP2005313466

申请日：2005-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  BENHASE MICHAEL THOMAS ,  BLOUNT LAWRENCE CARTER ,  HSU YU-CHENG ,  NAYAR NARESH

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5077 ,  G06F9/4881 ,  G06F2209/5014

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for managing access to a resource included in a data processing environment logically partitioned by a partition.
SOLUTION: This device, this program and this method assure a temporal period in which use of a resource by the partition is not forcibly excluded by a hypervisor. Inquiry communication transmitted by the partition urges the hypervisor to determine whether work for the hypervisor in a pending state or not. If not, the hypervisor transmits an assurance response for assuring the period of uninterrupted use of the resource by the partition.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于管理对由分区进行逻辑分区的数据处理环境中包括的资源的访问的改进方法。 解决方案：该设备，该程序和该方法确保了一个时间段，在该时间段内，分区的资源使用不被管理程序强制排除。 由分区发送的查询通信会敦促管理程序确定管理程序是否处于待处理状态。 如果没有，则管理程序发送保证响应，以确保分区不间断地使用资源的时间段。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008171428A

公开(公告)日：2008-07-24

申请号：JP2008001409

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FRAZIER GILES ROGER ,  CORRIGAN MICHAEL J ,  RICHARD LEWIS ARNT ,  ARMSTRONG WILLIAM JOSEPH ,  O'QUIN II JOHN THOMAS ,  NAYAR NARESH ,  MARCHINI TIMOTHY RICHARD ,  CATHY MAY

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/30181 ,  G06F9/468

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for selecting an architecture level to which a processor appears to conform in specification within a computing environment in order to achieve efficient program execution and migration among processor architectures with different levels.
SOLUTION: The method utilizes a processor compatibility register (PCR) that controls an architecture level that the processor appears to support. In one embodiment, the PCR is accessible only by super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program is designed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在计算环境中选择处理器看起来符合规范的体系结构级别的方法和系统，以便在具有不同级别的处理器架构之间实现有效的程序执行和迁移。 解决方案：该方法利用处理器兼容性寄存器（PCR）来控制处理器似乎支持的架构级别。 在一个实施方案中，PCR仅可由超级特权软件访问。 超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004303237A

公开(公告)日：2004-10-28

申请号：JP2004085678

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  ARNDT RICHARD LOUIS ,  NAYAR NARESH

IPC: G06F9/46 ,  G06F9/22 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45541 ,  G06F9/4812 ,  G06F9/5077

Abstract: PROBLEM TO BE SOLVED: To support virtual interrupts in a computer system that may include share processors with no changes to a logical partition's operating system.
SOLUTION: A set of virtual interrupt registers is created for each virtual processor in the system. A resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the viewpoint of the operating system, the interrupt processing when the operating system is running in a logical partition that may include shared processors and virtual interrupts is no different from the interrupt processing when the operating system is running in the computer system that only includes dedicated processor partitions.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2006302270A

公开(公告)日：2006-11-02

申请号：JP2006103737

申请日：2006-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  CORRIGAN MICHAEL J ,  NAYAR NARESH ,  SWANEY SCOTT B

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F1/14

Abstract: PROBLEM TO BE SOLVED: To provide a method for providing a virtual time base of a logically divided data processing system in a data processing system, equipment and a computer program product. SOLUTION: A time base is determined for each of a plurality of processor cores. With the use of the time base, the present time is shown to one of the processor cores of which time base is determined. In order that each of the processor cores can have its own copy of synchronized time base, the time bases of the processor cores are synchronized with each other. A virtual time base which is different from the synchronized time base, but which is synchronized with at least a part of the synchronized time base is generated. The processor core uses the virtual time base in place of the synchronized time base to show itself the present time. A part of the synchronized time base and the virtual time base is kept synchronized. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在数据处理系统，设备和计算机程序产品中提供逻辑划分的数据处理系统的虚拟时基的方法。 解决方案：为多个处理器核心中的每一个确定时基。 通过使用时基，将当前时间显示给确定时基的其中一个处理器核心。 为了使每个处理器核心具有自己的同步时基副本，处理器核心的时间基准彼此同步。 生成与同步时基不同但与同步时基的至少一部分同步的虚拟时基。 处理器核心使用虚拟时基代替同步的时基来显示当前时间。 同步时基和虚拟时基的一部分保持同步。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004326743A

公开(公告)日：2004-11-18

申请号：JP2004087908

申请日：2004-03-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM JOSEPH ,  LARSON DAVID ANTHONY ,  NAYAR NARESH

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48 ,  G06F13/24

CPC classification number: G06F9/45533 ,  G06F13/24

Abstract: PROBLEM TO BE SOLVED: To provide a method, system, and a program article of manufacture for processing virtual interrupts in a logically partitioned system. SOLUTION: An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logical partition may be utilized. Upon receiving a virtual interrupt, the virtual GIQ may examine the operating states of the associated virtual processors. In an effort to ensure the virtual interrupt is processed as quickly as possible, the virtual GIQ may present the virtual interrupt to one of the associated virtual processors determined to be in an operating state best suited for processing the virtual interrupt. COPYRIGHT: (C)2005,JPO&NCIPI