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    METHOD AND APPARATUS FOR ALLOCATING PROCESSOR RESOURCES IN A LOGICALLY PARTITIONED COMPUTER SYSTEM
    2.
    发明公开
    METHOD AND APPARATUS FOR ALLOCATING PROCESSOR RESOURCES IN A LOGICALLY PARTITIONED COMPUTER SYSTEM 审中-公开
    方法和设备的处理器资源在逻辑分区的计算机系统中分配

    公开(公告)号：EP1390839A4

    公开(公告)日：2007-12-12

    申请号：EP01995451

    申请日：2001-12-11

    Applicant: IBM

    Inventor： ARMSTRONG WILLIAM J ,  MANGES MARK GREGORY ,  NAYAR NARESH ,  SCHELL JEFFREY JAY ,  WILCOX CRAIG ALDEN

    IPC: G06F9/50

    CPC classification number: G06F9/5077 ,  G06F2209/5012

    Abstract: A processor allocation mechanism for a logically partitionable computer system allows an administrator to specify processing capability allocable to each partition as an equivalent number of processors (401), where the processing capability may be specified as a non-integer value. This processing capability value is unaffected by changes to the processing capability values of other partitions. The administrator may designate multiple sets of processors (402), assigning each physical processor of the system to a respective processor set (403). Each logical partition is constrained to execute in an assigned processor set (404), which may be shared by more than one partition. Preferably, the administrator may designate a logical partition as either capped, meaning that a partition can not use excess idle capacity of the processors, or uncapped, meaning that it can.

    Method for efficient virtual time base of scalable multi-processor computers, equipment, and program
    6.
    发明专利
    Method for efficient virtual time base of scalable multi-processor computers, equipment, and program 有权
    可扩展多处理器计算机，设备和程序的有效虚拟时基的方法

    公开(公告)号：JP2006302270A

    公开(公告)日：2006-11-02

    申请号：JP2006103737

    申请日：2006-04-05

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ARMSTRONG WILLIAM J ,  CORRIGAN MICHAEL J ,  NAYAR NARESH ,  SWANEY SCOTT B

    IPC: G06F9/46 ,  G06F9/52

    CPC classification number: G06F1/14

    Abstract: PROBLEM TO BE SOLVED: To provide a method for providing a virtual time base of a logically divided data processing system in a data processing system, equipment and a computer program product. SOLUTION: A time base is determined for each of a plurality of processor cores. With the use of the time base, the present time is shown to one of the processor cores of which time base is determined. In order that each of the processor cores can have its own copy of synchronized time base, the time bases of the processor cores are synchronized with each other. A virtual time base which is different from the synchronized time base, but which is synchronized with at least a part of the synchronized time base is generated. The processor core uses the virtual time base in place of the synchronized time base to show itself the present time. A part of the synchronized time base and the virtual time base is kept synchronized. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在数据处理系统，设备和计算机程序产品中提供逻辑划分的数据处理系统的虚拟时基的方法。 解决方案：为多个处理器核心中的每一个确定时基。 通过使用时基，将当前时间显示给确定时基的其中一个处理器核心。 为了使每个处理器核心具有自己的同步时基副本，处理器核心的时间基准彼此同步。 生成与同步时基不同但与同步时基的至少一部分同步的虚拟时基。 处理器核心使用虚拟时基代替同步的时基来显示当前时间。 同步时基和虚拟时基的一部分保持同步。 版权所有（C）2007，JPO＆INPIT

    MANAGEMENT OF SIMULTANEOUS USE LICENSE ON LOGICALLY PATITIONED COMPUTER
    7.
    发明专利
    MANAGEMENT OF SIMULTANEOUS USE LICENSE ON LOGICALLY PATITIONED COMPUTER 失效

    公开(公告)号：JP2000357086A

    公开(公告)日：2000-12-26

    申请号：JP2000143223

    申请日：2000-05-16

    Applicant: IBM

    Inventor： ARMSTRONG WILLIAM J ,  NARESH NEIYAA ,  KEVIN PATRICK SUTOMACCHAA

    IPC: G06F12/14 ,  G06F9/06 ,  G06F17/00 ,  G06F21/00 ,  G06F21/22 ,  G06F21/24

    Abstract: PROBLEM TO BE SOLVED: To obtain an improved method which manages the simultaneous use license and specially manages the number of simultaneous uses over multiple logical sections by tracking the simultaneous use of a computer over multiple logical sections. SOLUTION: License management is carried out by using >=1 license manager 90 arranged in respective logical sections 40, 42, and 44. Each license manager 90 has access to common service represented by a use tracker 92 and holds the counts of activity uses of all license computer programs to be tracked. A license manager 90 in each logical section processes a function of accepting or rejecting a request to execute the license application 94 in the section. For the purpose, each license manager 90 retrieves the instruction of the large-area counts of uses over all the logical sections on the computer 10.

    PROCESSOR RESET GENERATED THROUGH MEMORY ACCESS INTERRUPTION
    9.
    发明专利
    PROCESSOR RESET GENERATED THROUGH MEMORY ACCESS INTERRUPTION 失效

    公开(公告)号：JP2001022713A

    公开(公告)日：2001-01-26

    申请号：JP2000143160

    申请日：2000-05-16

    Applicant: IBM

    Inventor： TROY DAVID ARMSTRONG ,  ARMSTRONG WILLIAM J ,  NARESH NEIYAA ,  KENNETH CHARLES BOSSEN

    IPC: G06F11/30 ,  G06F1/24 ,  G06F11/07 ,  G06F12/10 ,  G06F15/177

    Abstract: PROBLEM TO BE SOLVED: To provide a device, a program product, and a method which make effective the resetting of a processor in multiprocessor environment by using a memory access interruption. SOLUTION: A source processor is allowed to start resetting a target processor by generating a reset request and a memory access interruption to the target processor. The target processor is constituted so as to detect the presence of a held reset request, specially, in the processing of a memory access interruption, and consequently the target process performs resetting operation in response to the detection of a request thereby.

    LOGICAL SECTION MANAGER AND METHOD
    10.
    发明专利
    LOGICAL SECTION MANAGER AND METHOD 失效

    公开(公告)号：JP2000353102A

    公开(公告)日：2000-12-19

    申请号：JP2000143282

    申请日：2000-05-16

    Applicant: IBM

    Inventor： TROY DAVID ARMSTRONG ,  ARMSTRONG WILLIAM J ,  CORIGAN MICHAEL JOSEPH ,  NARESH NEIYAA ,  THOMAS RENBAATO SAND ,  JEFFREY J SKILL ,  ERIKO TEIKARU ,  KENNETH CHARLES BOSSEN

    IPC: G06F9/06 ,  G06F9/00 ,  G06F9/455 ,  G06F9/46 ,  G06F15/00 ,  G06F15/173

    Abstract: PROBLEM TO BE SOLVED: To shorten the generation time of a partition manager by managing the use of computer system resources by multiple logical sections and including the partition manager including one call of an operating system present in a previously selected logical section. SOLUTION: A main memory 120 includes the partition manager 122 and manages a primary section 124 and one or more secondary sections 126, which are all logical sections. The primary section 124 includes an operating system 125 and the secondary sections 126 include an operating system 127. The partition manager 122 includes an interface 123 for the operating system 125 in the primary section 124. Thus, the partition manager 122 implements its section managing function by using a code which is already present in the operating system 125 instead of copying the code.

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