公开(公告)号：EP1849183A4

公开(公告)日：2010-09-01

申请号：EP06735050

申请日：2006-02-14

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

公开(公告)号：EP1856735A4

公开(公告)日：2009-07-15

申请号：EP06737610

申请日：2006-03-08

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

公开(公告)号：JPH11288930A

公开(公告)日：1999-10-19

申请号：JP1271499

申请日：1999-01-21

Applicant: IBM ,  SIEMENS AG ,  LAM RES CORP

Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

IPC: H01L21/31 ,  C23C16/40 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To improve gap-filling characteristics by performing the reaction and adhesion of an F-BPSG layer under specific ranges of pressure and temperature by the mixture of a reduced pressure chemical vapor growth process and the reactants of TEOS and FTES. SOLUTION: Orthotetraethyl silicate(TEOS), fluoroalkoxysilane(FTES) containing fluorine, boron and phosphor dopants, and an oxygen supply source are mixed with each another for reaction at a temperature of approximately 650-850 deg., under a pressure of approximately 0.5-5 torr in a chamber. Then, a fluorine dope BPSG layer (borophospho-silicate-glass) 22 that is generated by a reaction is allowed to adhere onto a semiconductor substrate 11 which is arranged in the chamber. Then, a layered semiconductor element is subjected to reflow at a temperature that is lower than approximately 800 deg.C, thus flattening the adhering layer and as a result filling the opening of a wafer 10 with a large aspect ratio and a small gap with the same adhesion/annealing temperature and the same dopant concentration of boron and phosphor.

公开(公告)号：WO2006096813A2

公开(公告)日：2006-09-14

申请号：PCT/US2006008449

申请日：2006-03-08

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L21/469 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

Abstract translation: 提供材料堆叠（12），其包括一个或多个膜（14），其具有大约IE-10m / sec或更大的裂纹速度和至少一个单层（16）在一个或多个膜内或直接接触一个或多个膜 （14），其中所述至少一个单层（16）将所述材料堆叠（12）的裂纹速度降低到小于1E-10m / sec的值。 一个或多个膜（14）不限于低k电介质，而是可以包括诸如金属的材料。 在优选实施例中，提供具有约3.0或更小的有效介电常数k的低k电介质堆叠（12），其中通过引入至少一个纳米层（16）来提高堆叠（12）的机械性能 ）到介电叠层（12）中。 在不显着增加叠层（12）内的薄膜的介电常数并且不需要对本发明的电介质叠层（12）进行任何后处理步骤的情况下，实现机械性能的改善。

公开(公告)号：WO2006088881A3

公开(公告)日：2007-01-18

申请号：PCT/US2006005204

申请日：2006-02-14

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter "SiCOH") in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, -CH 2 - crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH 3 +CH 2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH 3 bonding of greater than about 2.0, and a peak area for Si-O-Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Abstract translation: 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和更少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3 N 2 CH 2拉伸峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：DE102012219171A1

公开(公告)日：2013-05-08

申请号：DE102012219171

申请日：2012-10-22

Applicant: IBM

Inventor： NGUYEN SON V

IPC: H01L21/768 ,  H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: Mindestens eine metallische Adhäsionsschicht wird auf mindestens einer Cu-Fläche eines ersten Bauelement-Wafers gebildet. Ein zweiter Bauelement-Wafer mit einer weiteren Cu-Fläche wird über der Cu-Fläche des ersten Bauelement-Wafers und auf der mindestens einen metallischen Adhäsionsschicht positioniert. Der erste und der zweite Bauelement-Wafer werden dann zusammengebondet. Das Bonden beinhaltet das Erwärmen der Bauelement-Wafer auf eine Temperatur von weniger als 400°C mit oder ohne Anwendung eines äußerlich angewandten Drucks. Während des Erwärmens werden die beiden Cu-Flächen zusammengebondet und die mindestens eine metallische Adhäsionsschicht erhält Sauerstoffatome von den beiden Cu-Flächen und bildet mindestens eine Metalloxid-Bondschicht zwischen den Cu-Flächen.

公开(公告)号：CA1277031C

公开(公告)日：1990-11-27

申请号：CA534688

申请日：1987-04-14

Applicant: IBM

Inventor： FITZGERALD BRIAN F ,  NGUYEN KIM Y T ,  NGUYEN SON V

IPC: H01L27/10 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24 ,  G11C11/34

Abstract: HIGH DENSITY VERTICALLY STRUCTURED MEMORY A dynamic random access memory is provided wherein each cell has a storage capacitor and switching device and a bit/sense line or plate located along a sidewall of a trench formed in a semiconductor substrate. In a more particular structure of the cell, the trench width defines the length of the switching device, with the storage capacitor and a highly conductive bit/sense line being formed along opposite sidewalls of the trench. In an array of such cells, the highly conductive bit/sense line or plate interconnecting a large number of the cells of the array extends continuously from cell to cell within the trench at a sidewall thereof. Likewise, the storage capacitors of these many cells have a highly conductive common plate extending continuously within the trench at the opposite sidewall. BU-9-85-004

公开(公告)号：SG145626A1

公开(公告)日：2008-09-29

申请号：SG2008010068

申请日：2008-02-05

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： RESTAINO DARRYL D ,  WIDODO JOHNNY ,  BONILLA GRISELDA ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  KIM JAE H ,  LANE MICHAEL W ,  LIU XIAO H ,  NGUYEN SON V ,  SHAW THOMAS M

Abstract: BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS A chip is provided which includes a back-end-of-line ("BEOL") interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ("ILD") layers which include a dielectric material curable by ultraviolet ("UV") radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

公开(公告)号：DE69832035T2

公开(公告)日：2006-07-13

申请号：DE69832035

申请日：1998-12-07

Applicant: LAM RES CORP ,  IBM ,  SIEMENS AG

Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

IPC: C23C16/40 ,  H01L21/31 ,  C23C16/44 ,  H01L21/316

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. Preferably the glass deposition is performed at a temperature of about 750-850 DEG C and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

公开(公告)号：DE69832035D1

公开(公告)日：2005-12-01

申请号：DE69832035

申请日：1998-12-07

Applicant: LAM RES CORP ,  IBM ,  SIEMENS AG

Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

IPC: H01L21/31 ,  C23C16/40 ,  H01L21/316 ,  C23C16/44

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. Preferably the glass deposition is performed at a temperature of about 750-850 DEG C and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.