公开(公告)号：JPH08115988A

公开(公告)日：1996-05-07

申请号：JP25618895

申请日：1995-10-03

Applicant: IBM

Inventor： JIYOISU ERIZABESU AKOOSERA ,  KIYARORU GARI ,  RUISU RUU CHIEN SUU ,  SEIKI OGURA ,  NIBUO ROBUEDOO ,  JIYOSEFU FURANSHISU SHIEPAADO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve packaging density, performance, and manufacturing yield in an electrically erasable EEPROM by confining a floating gate structure between separation structures that are covered with a thin nitride layer. SOLUTION: A floating gate 24 is entrapped by making flat up to the surface of nitride layer by the self-limiting chemical/mechanical polishing process. Then, the connection of a gate oxide 25 and a control electrode 26 is formed on a nearly flat surface. Since a halsh topography on a surface where the connection is formed can be avoided, a low-resistance connection including a metallic connection can be formed appropriately, thus reducing the transistor of a memory cell.